From d6736384b2bb280ec12d472cac6eb25a70b4af60 Mon Sep 17 00:00:00 2001
From: Gene Wu <Gene.Wu@arm.com>
Date: Mon, 23 Aug 2010 11:18:41 -0500
Subject: MEM: Make CLREX a first class request operation and clear locks in
 caches when it in received

---
 src/mem/cache/cache_impl.hh  | 28 +++++++++++++++++-----------
 src/mem/cache/tags/base.hh   |  6 ++++++
 src/mem/cache/tags/fa_lru.cc |  8 ++++++++
 src/mem/cache/tags/fa_lru.hh |  6 ++++++
 src/mem/cache/tags/iic.cc    |  8 ++++++++
 src/mem/cache/tags/iic.hh    |  6 ++++++
 src/mem/cache/tags/lru.cc    |  8 ++++++++
 src/mem/cache/tags/lru.hh    |  5 +++++
 8 files changed, 64 insertions(+), 11 deletions(-)

(limited to 'src/mem/cache')

diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index e472b2601..d471b293a 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -273,12 +273,14 @@ bool
 Cache<TagStore>::access(PacketPtr pkt, BlkType *&blk,
                         int &lat, PacketList &writebacks)
 {
-    int id = pkt->req->hasContextId() ? pkt->req->contextId() : -1;
-    blk = tags->accessBlock(pkt->getAddr(), lat, id);
-
-    if (pkt->req->isUncacheable())  {
-        if (blk != NULL) {
-            tags->invalidateBlk(blk);
+    if (pkt->req->isUncacheable()) {
+        if (pkt->req->isClrex()) {
+            tags->clearLocks();
+        } else {
+           blk = tags->findBlock(pkt->getAddr());
+           if (blk != NULL) {
+               tags->invalidateBlk(blk);
+           }
         }
 
         blk = NULL;
@@ -286,6 +288,8 @@ Cache<TagStore>::access(PacketPtr pkt, BlkType *&blk,
         return false;
     }
 
+    int id = pkt->req->hasContextId() ? pkt->req->contextId() : -1;
+    blk = tags->accessBlock(pkt->getAddr(), lat, id);
 
     DPRINTF(Cache, "%s%s %x %s\n", pkt->cmdString(),
             pkt->req->isInstFetch() ? " (ifetch)" : "",
@@ -410,11 +414,13 @@ Cache<TagStore>::timingAccess(PacketPtr pkt)
     }
 
     if (pkt->req->isUncacheable()) {
-        int lat = hitLatency;
-        int id = pkt->req->hasContextId() ? pkt->req->contextId() : -1;
-        BlkType *blk = tags->accessBlock(pkt->getAddr(), lat, id);
-        if (blk != NULL) {
-            tags->invalidateBlk(blk);
+        if (pkt->req->isClrex()) {
+            tags->clearLocks();
+        } else {
+            BlkType *blk = tags->findBlock(pkt->getAddr());
+            if (blk != NULL) {
+                tags->invalidateBlk(blk);
+            }
         }
 
         // writes go in write buffer, reads use MSHR
diff --git a/src/mem/cache/tags/base.hh b/src/mem/cache/tags/base.hh
index fc8470290..62ae4a032 100644
--- a/src/mem/cache/tags/base.hh
+++ b/src/mem/cache/tags/base.hh
@@ -140,6 +140,12 @@ class BaseTags
      * exits.
      */
     virtual void cleanupRefs() {}
+
+    /**
+     *iterated through all blocks and clear all locks
+     *Needed to clear all lock tracking at once
+     */
+    virtual void clearLocks() {}
 };
 
 class BaseTagsCallback : public Callback
diff --git a/src/mem/cache/tags/fa_lru.cc b/src/mem/cache/tags/fa_lru.cc
index d13ba4973..4d1c2175f 100644
--- a/src/mem/cache/tags/fa_lru.cc
+++ b/src/mem/cache/tags/fa_lru.cc
@@ -286,3 +286,11 @@ FALRU::check()
     }
     return true;
 }
+
+void
+FALRU::clearLocks()
+{
+    for (int i = 0; i < numBlocks; i++){
+        blks[i].clearLoadLocks();
+    }
+}
diff --git a/src/mem/cache/tags/fa_lru.hh b/src/mem/cache/tags/fa_lru.hh
index 5047da12a..94ffeaa58 100644
--- a/src/mem/cache/tags/fa_lru.hh
+++ b/src/mem/cache/tags/fa_lru.hh
@@ -280,6 +280,12 @@ public:
     {
         return (tag);
     }
+
+    /**
+     *iterated through all blocks and clear all locks
+     *Needed to clear all lock tracking at once
+     */
+    virtual void clearLocks();
 };
 
 #endif // __MEM_CACHE_TAGS_FA_LRU_HH__
diff --git a/src/mem/cache/tags/iic.cc b/src/mem/cache/tags/iic.cc
index f9afa5839..b5bd66366 100644
--- a/src/mem/cache/tags/iic.cc
+++ b/src/mem/cache/tags/iic.cc
@@ -631,6 +631,14 @@ IIC::invalidateBlk(IIC::BlkType *tag_ptr)
     }
 }
 
+void
+IIC::clearLocks()
+{
+    for (int i = 0; i < numTags; i++){
+        tagStore[i].clearLoadLocks();
+    }
+}
+
 void
 IIC::cleanupRefs()
 {
diff --git a/src/mem/cache/tags/iic.hh b/src/mem/cache/tags/iic.hh
index 5b12128c6..5553b8ca3 100644
--- a/src/mem/cache/tags/iic.hh
+++ b/src/mem/cache/tags/iic.hh
@@ -439,6 +439,11 @@ class IIC : public BaseTags
     IICTag* findVictim(Addr addr, PacketList &writebacks);
 
     void insertBlock(Addr addr, BlkType *blk, int context_src);
+    /**
+     *iterated through all blocks and clear all locks
+     *Needed to clear all lock tracking at once
+     */
+    virtual void clearLocks();
 
     /**
      * Called at end of simulation to complete average block reference stats.
@@ -497,6 +502,7 @@ private:
      * @param data_ptr The data block to free.
      */
     void freeDataBlock(unsigned long data_ptr);
+
 };
 #endif // __IIC_HH__
 
diff --git a/src/mem/cache/tags/lru.cc b/src/mem/cache/tags/lru.cc
index 0667c5428..a99936abf 100644
--- a/src/mem/cache/tags/lru.cc
+++ b/src/mem/cache/tags/lru.cc
@@ -216,6 +216,14 @@ LRU::invalidateBlk(BlkType *blk)
     }
 }
 
+void
+LRU::clearLocks()
+{
+    for (int i = 0; i < numBlocks; i++){
+        blks[i].clearLoadLocks();
+    }
+}
+
 void
 LRU::cleanupRefs()
 {
diff --git a/src/mem/cache/tags/lru.hh b/src/mem/cache/tags/lru.hh
index be8d75b5a..ff9811046 100644
--- a/src/mem/cache/tags/lru.hh
+++ b/src/mem/cache/tags/lru.hh
@@ -224,6 +224,11 @@ public:
     {
         return hitLatency;
     }
+    /**
+     *iterated through all blocks and clear all locks
+     *Needed to clear all lock tracking at once
+     */
+    virtual void clearLocks();
 
     /**
      * Called at end of simulation to complete average block reference stats.
-- 
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