From eaa994e7f6c12f6dc3e17836052f76a5ce9bdc01 Mon Sep 17 00:00:00 2001
From: Ali Saidi <Ali.Saidi@ARM.com>
Date: Fri, 9 Mar 2012 09:59:25 -0500
Subject: cache: Allow main memory to be at disjoint address ranges.

---
 src/mem/cache/BaseCache.py  | 2 +-
 src/mem/cache/base.cc       | 2 +-
 src/mem/cache/base.hh       | 4 ++--
 src/mem/cache/cache_impl.hh | 4 +---
 4 files changed, 5 insertions(+), 7 deletions(-)

(limited to 'src/mem/cache')

diff --git a/src/mem/cache/BaseCache.py b/src/mem/cache/BaseCache.py
index adc48a461..83b3c70c2 100644
--- a/src/mem/cache/BaseCache.py
+++ b/src/mem/cache/BaseCache.py
@@ -60,5 +60,5 @@ class BaseCache(MemObject):
     prefetcher = Param.BasePrefetcher(NULL,"Prefetcher attached to cache")
     cpu_side = SlavePort("Port on side closer to CPU")
     mem_side = MasterPort("Port on side closer to MEM")
-    addr_range = Param.AddrRange(AllMemory, "The address range for the CPU-side port")
+    addr_ranges = VectorParam.AddrRange([AllMemory], "The address range for the CPU-side port")
     system = Param.System(Parent.any, "System we belong to")
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index c7c213cc6..fb2757616 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -83,7 +83,7 @@ BaseCache::BaseCache(const Params *p)
       noTargetMSHR(NULL),
       missCount(p->max_miss_count),
       drainEvent(NULL),
-      addrRange(p->addr_range),
+      addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()),
       system(p->system)
 {
 }
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index e522bc0c9..2a79fb354 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -269,7 +269,7 @@ class BaseCache : public MemObject
     /**
      * The address range to which the cache responds on the CPU side.
      * Normally this is all possible memory addresses. */
-    Range<Addr> addrRange;
+    AddrRangeList addrRanges;
 
   public:
     /** System we are currently operating in. */
@@ -439,7 +439,7 @@ class BaseCache : public MemObject
     Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); }
 
 
-    const Range<Addr> &getAddrRange() const { return addrRange; }
+    const AddrRangeList &getAddrRanges() const { return addrRanges; }
 
     MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus)
     {
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 024ae3297..f6efc3fb8 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -1556,9 +1556,7 @@ template<class TagStore>
 AddrRangeList
 Cache<TagStore>::CpuSidePort::getAddrRanges()
 {
-    AddrRangeList ranges;
-    ranges.push_back(cache->getAddrRange());
-    return ranges;
+    return cache->getAddrRanges();
 }
 
 template<class TagStore>
-- 
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