From fd678694ee6bf9defe10d76e01c3e728a25d1871 Mon Sep 17 00:00:00 2001
From: Gabe Black <gabeblack@google.com>
Date: Fri, 5 Jan 2018 23:52:29 -0800
Subject: x86, mem: Get rid of PageTableOps::getBasePtr.

Pass this constant into the page table constructor.

Change-Id: Icbf730f18d9dfcfebd10a196f7f799514728b0fb
Reviewed-on: https://gem5-review.googlesource.com/7345
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
---
 src/mem/multi_level_page_table_impl.hh | 10 ++--------
 1 file changed, 2 insertions(+), 8 deletions(-)

(limited to 'src/mem/multi_level_page_table_impl.hh')

diff --git a/src/mem/multi_level_page_table_impl.hh b/src/mem/multi_level_page_table_impl.hh
index 2d7ddc4e4..3356c9ea2 100644
--- a/src/mem/multi_level_page_table_impl.hh
+++ b/src/mem/multi_level_page_table_impl.hh
@@ -47,10 +47,9 @@ using namespace TheISA;
 template <class ISAOps>
 MultiLevelPageTable<ISAOps>::MultiLevelPageTable(
         const std::string &__name, uint64_t _pid, System *_sys,
-        Addr pageSize, const std::vector<uint8_t> &layout)
+        Addr pageSize, const std::vector<uint8_t> &layout, Addr _basePtr)
     : EmulationPageTable(__name, _pid, pageSize), system(_sys),
-    logLevelSize(layout),
-    numLevels(logLevelSize.size())
+    basePtr(_basePtr), logLevelSize(layout), numLevels(logLevelSize.size())
 {
 }
 
@@ -63,11 +62,6 @@ template <class ISAOps>
 void
 MultiLevelPageTable<ISAOps>::initState(ThreadContext* tc)
 {
-    basePtr = pTableISAOps.getBasePtr(tc);
-    if (basePtr == 0)
-        basePtr++;
-    DPRINTF(MMU, "basePtr: %d\n", basePtr);
-
     system->pagePtr = basePtr;
 
     /* setting first level of the page table */
-- 
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