From 12497284949cb5418e6bc403723c034aee655666 Mon Sep 17 00:00:00 2001
From: Steve Reinhardt <steve.reinhardt@amd.com>
Date: Thu, 9 Sep 2010 14:40:19 -0400
Subject: cache: fail SC when invalidated while waiting for bus Corrects an
 oversight in cset f97b62be544f.  The fix there only failed queued
 SCUpgradeReq packets that encountered an invalidation, which meant that the
 upgrade had to reach the L2 cache.  To handle pending requests in the L1 we
 must similarly fail StoreCondReq packets too.

---
 src/mem/packet.cc | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'src/mem/packet.cc')

diff --git a/src/mem/packet.cc b/src/mem/packet.cc
index 5eb2ecc4b..d0b1fed83 100644
--- a/src/mem/packet.cc
+++ b/src/mem/packet.cc
@@ -123,6 +123,10 @@ MemCmd::commandInfo[] =
     { SET6(IsWrite, NeedsExclusive, IsLlsc,
            IsRequest, NeedsResponse, HasData),
             StoreCondResp, "StoreCondReq" },
+    /* StoreCondFailReq: generates failing StoreCondResp ASAP */
+    { SET6(IsWrite, NeedsExclusive, IsLlsc,
+           IsRequest, NeedsResponse, HasData),
+            StoreCondResp, "StoreCondFailReq" },
     /* StoreCondResp */
     { SET4(IsWrite, NeedsExclusive, IsLlsc, IsResponse),
             InvalidCmd, "StoreCondResp" },
-- 
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