From 57f2b7db11c9a16f3104588c137e6246bd124041 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Wed, 16 Jun 2010 15:25:57 -0700 Subject: cache: fix dirty bit setting Only set the dirty bit when we actually write to a block (not if we thought we might but didn't, as in a failed SC or CAS). This requires makeing sure the dirty bit stays set when we get an exclusive (writable) copy in a cache-to-cache transfer from another owner, which n turn requires copying the mem-inhibit flag from timing-mode requests to their associated responses. --- src/mem/packet.hh | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/mem/packet.hh') diff --git a/src/mem/packet.hh b/src/mem/packet.hh index e7a5335a8..17af558b5 100644 --- a/src/mem/packet.hh +++ b/src/mem/packet.hh @@ -559,6 +559,10 @@ class Packet : public FastAlloc, public Printable origCmd = cmd; cmd = cmd.responseCommand(); + // responses are never express, even if the snoop that + // triggered them was + flags.clear(EXPRESS_SNOOP); + dest = src; flags.set(VALID_DST, flags.isSet(VALID_SRC)); flags.clear(VALID_SRC); -- cgit v1.2.3