From a17afb1649e26c248dc4a61e4a0ef6671785e992 Mon Sep 17 00:00:00 2001 From: Ron Dreslinski Date: Fri, 13 Oct 2006 15:47:05 -0400 Subject: Fix for DMA's in FS caches. Fix CSHR's for flow control. Fix for Bus Bridges reusing packets (clean flags up) Now both timing/atomic caches with MOESI in UP fail at same point. src/dev/io_device.hh: DMA's should send WriteInvalidates src/mem/bridge.cc: Reusing packet, clean flags in the packet set by bus. src/mem/cache/base_cache.cc: src/mem/cache/base_cache.hh: src/mem/cache/cache.hh: src/mem/cache/cache_impl.hh: src/mem/cache/coherence/simple_coherence.hh: src/mem/cache/coherence/uni_coherence.cc: src/mem/cache/coherence/uni_coherence.hh: Fix CSHR's for flow control. src/mem/packet.hh: Make a writeInvalidateResp, since the DMA expects responses to it's writes --HG-- extra : convert_revision : 59fd6658bcc0d076f4b143169caca946472a86cd --- src/mem/packet.hh | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'src/mem/packet.hh') diff --git a/src/mem/packet.hh b/src/mem/packet.hh index 48b32ec47..319a4e534 100644 --- a/src/mem/packet.hh +++ b/src/mem/packet.hh @@ -202,7 +202,9 @@ class Packet HardPFResp = IsRead | IsResponse | IsHWPrefetch | NeedsResponse | HasData, InvalidateReq = IsInvalidate | IsRequest, - WriteInvalidateReq = IsWrite | IsInvalidate | IsRequest | HasData, + WriteInvalidateReq = IsWrite | IsInvalidate | IsRequest + | HasData | NeedsResponse, + WriteInvalidateResp = IsWrite | IsInvalidate | IsRequest | NeedsResponse, UpgradeReq = IsInvalidate | IsRequest | IsUpgrade, ReadExReq = IsRead | IsInvalidate | IsRequest | NeedsResponse, ReadExResp = IsRead | IsInvalidate | IsResponse -- cgit v1.2.3