From 4e8d2d1593475008b926829e6944a59963166079 Mon Sep 17 00:00:00 2001
From: Ali Saidi <saidi@eecs.umich.edu>
Date: Fri, 2 Mar 2007 22:34:51 -0500
Subject: make ldtw(a) -- Twin 32 bit load work correctly -- by doing it the
 same way as the twin 64 bit loads

src/arch/isa_parser.py:
src/arch/sparc/isa/decoder.isa:
src/arch/sparc/isa/operands.isa:
src/base/bigint.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
src/mem/packet_access.hh:
    make ldtw(a) Twin 32 bit load work correctly

--HG--
extra : convert_revision : 2646b269d58cc1774e896065875a56cf5e313b42
---
 src/mem/packet_access.hh | 12 ++++++++++++
 1 file changed, 12 insertions(+)

(limited to 'src/mem/packet_access.hh')

diff --git a/src/mem/packet_access.hh b/src/mem/packet_access.hh
index 882aa98d0..552b6dd27 100644
--- a/src/mem/packet_access.hh
+++ b/src/mem/packet_access.hh
@@ -53,6 +53,18 @@ Packet::get()
     return d;
 }
 
+template<>
+inline Twin32_t
+Packet::get()
+{
+    Twin32_t d;
+    assert(staticData || dynamicData);
+    assert(sizeof(Twin32_t) <= size);
+    d.a = TheISA::gtoh(*(uint32_t*)data);
+    d.b = TheISA::gtoh(*((uint32_t*)data + 1));
+    return d;
+}
+
 
 /** return the value of what is pointed to in the packet. */
 template <typename T>
-- 
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