From 2b62fec3590024a7ce82ef5d4647397d37ed37eb Mon Sep 17 00:00:00 2001
From: Iru Cai <mytbk920423@gmail.com>
Date: Sat, 11 May 2019 21:41:14 +0800
Subject: try not expose if L1 hit

---
 src/mem/protocol/MESI_Two_Level-L1cache.sm | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/mem/protocol/MESI_Two_Level-L1cache.sm')

diff --git a/src/mem/protocol/MESI_Two_Level-L1cache.sm b/src/mem/protocol/MESI_Two_Level-L1cache.sm
index 846af7da5..f5feb7e23 100644
--- a/src/mem/protocol/MESI_Two_Level-L1cache.sm
+++ b/src/mem/protocol/MESI_Two_Level-L1cache.sm
@@ -1323,6 +1323,7 @@ machine(MachineType:L1Cache, "MESI Directory L1 Cache CMP")
 
   transition({S,E,M}, SpecLoad) {
     h_spec_load_hit;
+    uu_profileDataHit;
     k_popMandatoryQueue;
   }
 
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