From 6599dd87c8332e4db3d898c9a28531ce2740c37f Mon Sep 17 00:00:00 2001 From: Marco Elver Date: Sun, 7 Jun 2015 14:02:40 -0500 Subject: ruby: Fix MESI consistency bug Fixes missed forward eviction to CPU. With the O3CPU this can lead to load-load reordering, as the LQ is never notified of the invalidate. Committed by: Nilay Vaish --- src/mem/protocol/MESI_Two_Level-L1cache.sm | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mem/protocol/MESI_Two_Level-L1cache.sm') diff --git a/src/mem/protocol/MESI_Two_Level-L1cache.sm b/src/mem/protocol/MESI_Two_Level-L1cache.sm index b449c4f2b..4f9928bf1 100644 --- a/src/mem/protocol/MESI_Two_Level-L1cache.sm +++ b/src/mem/protocol/MESI_Two_Level-L1cache.sm @@ -1341,6 +1341,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") // transitions from SM transition(SM, Inv, IM) { + forward_eviction_to_cpu; fi_sendInvAck; dg_invalidate_sc; l_popRequestQueue; -- cgit v1.2.3