From b0e609d5cf6961bb9b3f12065659e1c42c13ef06 Mon Sep 17 00:00:00 2001
From: Iru Cai <mytbk920423@gmail.com>
Date: Sun, 12 May 2019 14:34:21 +0800
Subject: only spec load when hit

---
 src/mem/protocol/MESI_Two_Level-L1cache.sm | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

(limited to 'src/mem/protocol/MESI_Two_Level-L1cache.sm')

diff --git a/src/mem/protocol/MESI_Two_Level-L1cache.sm b/src/mem/protocol/MESI_Two_Level-L1cache.sm
index f5feb7e23..8496fda61 100644
--- a/src/mem/protocol/MESI_Two_Level-L1cache.sm
+++ b/src/mem/protocol/MESI_Two_Level-L1cache.sm
@@ -981,6 +981,12 @@ machine(MachineType:L1Cache, "MESI Directory L1 Cache CMP")
     sequencer.readCallback(address, cache_entry.DataBlk);
   }
 
+  action(h_spec_load_miss, "hsm",
+         desc="Notify sequencer the spec load misses.")
+  {
+    sequencer.readCallback(address, cache_entry.DataBlk, true);
+  }
+
   action(h_ifetch_hit, "hi", desc="Notify sequencer the instruction fetch completed.")
   {
     assert(is_valid(cache_entry));
@@ -1222,8 +1228,7 @@ machine(MachineType:L1Cache, "MESI Directory L1 Cache CMP")
   }
 
   transition({NP,I}, SpecLoad, IX) {
-    iw_allocateTBEWithoutCacheEntry;
-    as_issueGETSPEC;
+    h_spec_load_miss;
     k_popMandatoryQueue;
   }
 
-- 
cgit v1.2.3