From cee8faaad066cda6710904b5190e7287ff9356af Mon Sep 17 00:00:00 2001 From: Nilay Vaish Date: Mon, 1 Sep 2014 16:55:45 -0500 Subject: ruby: slicc: change the way configurable members are specified There are two changes this patch makes to the way configurable members of a state machine are specified in SLICC. The first change is that the data member declarations will need to be separated by a semi-colon instead of a comma. Secondly, the default value to be assigned would now use SLICC's assignment operator i.e. ':='. --- src/mem/protocol/MESI_Two_Level-L1cache.sm | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'src/mem/protocol/MESI_Two_Level-L1cache.sm') diff --git a/src/mem/protocol/MESI_Two_Level-L1cache.sm b/src/mem/protocol/MESI_Two_Level-L1cache.sm index a202a8deb..96c1699b7 100644 --- a/src/mem/protocol/MESI_Two_Level-L1cache.sm +++ b/src/mem/protocol/MESI_Two_Level-L1cache.sm @@ -27,16 +27,16 @@ */ machine(L1Cache, "MESI Directory L1 Cache CMP") - : Sequencer * sequencer, - CacheMemory * L1Icache, - CacheMemory * L1Dcache, - Prefetcher * prefetcher = 'NULL', - int l2_select_num_bits, - Cycles l1_request_latency = 2, - Cycles l1_response_latency = 2, - Cycles to_l2_latency = 1, - bool send_evictions, - bool enable_prefetch = "False" + : Sequencer * sequencer; + CacheMemory * L1Icache; + CacheMemory * L1Dcache; + Prefetcher * prefetcher; + int l2_select_num_bits; + Cycles l1_request_latency := 2; + Cycles l1_response_latency := 2; + Cycles to_l2_latency := 1; + bool send_evictions; + bool enable_prefetch := "False"; { // NODE L1 CACHE // From this node's L1 cache TO the network -- cgit v1.2.3