From 48e43c9ad1cd292b494f3d05f9d13845dd1a6d1e Mon Sep 17 00:00:00 2001
From: Michael LeBeane <michael.lebeane@amd.com>
Date: Wed, 26 Oct 2016 22:48:37 -0400
Subject: ruby: Allow multiple outstanding DMA requests DMA sequencers and
 protocols can currently only issue one DMA access at a time. This patch
 implements the necessary functionality to support multiple outstanding DMA
 requests in Ruby.

---
 src/mem/protocol/MESI_Two_Level-dma.sm | 84 +++++++++++++++++++++++++++++-----
 1 file changed, 72 insertions(+), 12 deletions(-)

(limited to 'src/mem/protocol/MESI_Two_Level-dma.sm')

diff --git a/src/mem/protocol/MESI_Two_Level-dma.sm b/src/mem/protocol/MESI_Two_Level-dma.sm
index 68cb7e968..ecda3bd03 100644
--- a/src/mem/protocol/MESI_Two_Level-dma.sm
+++ b/src/mem/protocol/MESI_Two_Level-dma.sm
@@ -50,15 +50,38 @@ machine(MachineType:DMA, "DMA Controller")
     Ack,          desc="DMA write to memory completed";
   }
 
-  State cur_state;
+  structure(TBE, desc="...") {
+    State TBEState,    desc="Transient state";
+    DataBlock DataBlk, desc="Data";
+  }
+
+  structure(TBETable, external = "yes") {
+    TBE lookup(Addr);
+    void allocate(Addr);
+    void deallocate(Addr);
+    bool isPresent(Addr);
+  }
+
+  void set_tbe(TBE b);
+  void unset_tbe();
+  void wakeUpAllBuffers();
+
+  TBETable TBEs, template="<DMA_TBE>", constructor="m_number_of_TBEs";
+
   Tick clockEdge();
 
-  State getState(Addr addr) {
-    return cur_state;
+  State getState(TBE tbe, Addr addr) {
+    if (is_valid(tbe)) {
+        return tbe.TBEState;
+    } else {
+        return State:READY;
+    }
   }
 
-  void setState(Addr addr, State state) {
-    cur_state := state;
+  void setState(TBE tbe, Addr addr, State state) {
+    if (is_valid(tbe)) {
+        tbe.TBEState := state;
+    }
   }
 
   AccessPermission getAccessPermission(Addr addr) {
@@ -82,9 +105,9 @@ machine(MachineType:DMA, "DMA Controller")
     if (dmaRequestQueue_in.isReady(clockEdge())) {
       peek(dmaRequestQueue_in, SequencerMsg) {
         if (in_msg.Type == SequencerRequestType:LD ) {
-          trigger(Event:ReadRequest, in_msg.LineAddress);
+          trigger(Event:ReadRequest, in_msg.LineAddress, TBEs[in_msg.LineAddress]);
         } else if (in_msg.Type == SequencerRequestType:ST) {
-          trigger(Event:WriteRequest, in_msg.LineAddress);
+          trigger(Event:WriteRequest, in_msg.LineAddress, TBEs[in_msg.LineAddress]);
         } else {
           error("Invalid request type");
         }
@@ -96,9 +119,11 @@ machine(MachineType:DMA, "DMA Controller")
     if (dmaResponseQueue_in.isReady(clockEdge())) {
       peek( dmaResponseQueue_in, ResponseMsg) {
         if (in_msg.Type == CoherenceResponseType:ACK) {
-          trigger(Event:Ack, makeLineAddress(in_msg.addr));
+          trigger(Event:Ack, makeLineAddress(in_msg.addr),
+                  TBEs[makeLineAddress(in_msg.addr)]);
         } else if (in_msg.Type == CoherenceResponseType:DATA) {
-          trigger(Event:Data, makeLineAddress(in_msg.addr));
+          trigger(Event:Data, makeLineAddress(in_msg.addr),
+                  TBEs[makeLineAddress(in_msg.addr)]);
         } else {
           error("Invalid response type");
         }
@@ -133,15 +158,30 @@ machine(MachineType:DMA, "DMA Controller")
   }
 
   action(a_ackCallback, "a", desc="Notify dma controller that write request completed") {
-    dma_sequencer.ackCallback();
+    dma_sequencer.ackCallback(address);
   }
 
   action(d_dataCallback, "d", desc="Write data to dma sequencer") {
-    peek (dmaResponseQueue_in, ResponseMsg) {
-      dma_sequencer.dataCallback(in_msg.DataBlk);
+    dma_sequencer.dataCallback(tbe.DataBlk, address);
+  }
+
+  action(t_updateTBEData, "t", desc="Update TBE Data") {
+    assert(is_valid(tbe));
+    peek( dmaResponseQueue_in, ResponseMsg) {
+        tbe.DataBlk := in_msg.DataBlk;
     }
   }
 
+  action(v_allocateTBE, "v", desc="Allocate TBE entry") {
+    TBEs.allocate(address);
+    set_tbe(TBEs[address]);
+  }
+
+  action(w_deallocateTBE, "w", desc="Deallocate TBE entry") {
+    TBEs.deallocate(address);
+    unset_tbe();
+  }
+
   action(p_popRequestQueue, "p", desc="Pop request queue") {
     dmaRequestQueue_in.dequeue(clockEdge());
   }
@@ -150,23 +190,43 @@ machine(MachineType:DMA, "DMA Controller")
     dmaResponseQueue_in.dequeue(clockEdge());
   }
 
+  action(zz_stallAndWaitRequestQueue, "zz", desc="...") {
+    stall_and_wait(dmaRequestQueue_in, address);
+  }
+
+  action(wkad_wakeUpAllDependents, "wkad", desc="wake-up all dependents") {
+    wakeUpAllBuffers();
+  }
+
   transition(READY, ReadRequest, BUSY_RD) {
+    v_allocateTBE;
     s_sendReadRequest;
     p_popRequestQueue;
   }
 
   transition(READY, WriteRequest, BUSY_WR) {
+    v_allocateTBE;
     s_sendWriteRequest;
     p_popRequestQueue;
   }
 
   transition(BUSY_RD, Data, READY) {
+    t_updateTBEData;
     d_dataCallback;
+    w_deallocateTBE;
     p_popResponseQueue;
+    wkad_wakeUpAllDependents;
   }
 
   transition(BUSY_WR, Ack, READY) {
     a_ackCallback;
+    w_deallocateTBE;
     p_popResponseQueue;
+    wkad_wakeUpAllDependents;
   }
+
+  transition({BUSY_RD,BUSY_WR}, {ReadRequest,WriteRequest}) {
+     zz_stallAndWaitRequestQueue;
+  }
+
 }
-- 
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