From 07ea0891f1699f6194a05516948ce3824fb8fb38 Mon Sep 17 00:00:00 2001 From: Derek Hower Date: Tue, 19 Jan 2010 17:11:36 -0600 Subject: ruby: new atomics implementation This patch changes the way that Ruby handles atomic RMW instructions. This implementation, unlike the prior one, is protocol independent. It works by locking an address from the sequencer immediately after the read portion of an RMW completes. When that address is locked, the coherence controller will only satisfy requests coming from one port (e.g., the mandatory queue) and will ignore all others. After the write portion completed, the line is unlocked. This should also work with multi-line atomics, as long as the blocks are always acquired in the same order. --- src/mem/protocol/MOESI_CMP_directory-L1cache.sm | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/mem/protocol/MOESI_CMP_directory-L1cache.sm') diff --git a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm index db2efd3e7..f6b1d4f38 100644 --- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm +++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm @@ -306,7 +306,7 @@ machine(L1Cache, "Directory protocol") // Request Network in_port(requestNetwork_in, RequestMsg, requestToL1Cache) { if (requestNetwork_in.isReady()) { - peek(requestNetwork_in, RequestMsg) { + peek(requestNetwork_in, RequestMsg, block_on="Address") { assert(in_msg.Destination.isElement(machineID)); DEBUG_EXPR("MRM_DEBUG: L1 received"); DEBUG_EXPR(in_msg.Type); @@ -338,7 +338,7 @@ if (in_msg.Type == CoherenceRequestType:GETX || in_msg.Type == CoherenceRequestT // Response Network in_port(responseToL1Cache_in, ResponseMsg, responseToL1Cache) { if (responseToL1Cache_in.isReady()) { - peek(responseToL1Cache_in, ResponseMsg) { + peek(responseToL1Cache_in, ResponseMsg, block_on="Address") { if (in_msg.Type == CoherenceResponseType:ACK) { trigger(Event:Ack, in_msg.Address); } else if (in_msg.Type == CoherenceResponseType:DATA) { @@ -356,7 +356,7 @@ if (in_msg.Type == CoherenceRequestType:GETX || in_msg.Type == CoherenceRequestT // Mandatory Queue betweens Node's CPU and it's L1 caches in_port(mandatoryQueue_in, CacheMsg, mandatoryQueue, desc="...") { if (mandatoryQueue_in.isReady()) { - peek(mandatoryQueue_in, CacheMsg) { + peek(mandatoryQueue_in, CacheMsg, block_on="LineAddress") { // Check for data access to blocks in I-cache and ifetchs to blocks in D-cache -- cgit v1.2.3