From 905c0b347c785d07b606b6a9f3c6bbdf8ebe96a7 Mon Sep 17 00:00:00 2001 From: Joel Hestness Date: Fri, 14 Aug 2015 00:19:45 -0500 Subject: ruby: Protocol changes for SimObject MessageBuffers --- src/mem/protocol/MOESI_CMP_directory-dma.sm | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'src/mem/protocol/MOESI_CMP_directory-dma.sm') diff --git a/src/mem/protocol/MOESI_CMP_directory-dma.sm b/src/mem/protocol/MOESI_CMP_directory-dma.sm index d7e3a02d9..8aa7a5830 100644 --- a/src/mem/protocol/MOESI_CMP_directory-dma.sm +++ b/src/mem/protocol/MOESI_CMP_directory-dma.sm @@ -33,12 +33,12 @@ machine(DMA, "DMA Controller") Cycles response_latency := 14; MessageBuffer * responseFromDir, network="From", virtual_network="2", - ordered="false", vnet_type="response"; + vnet_type="response"; MessageBuffer * reqToDir, network="To", virtual_network="1", - ordered="false", vnet_type="request"; + vnet_type="request"; MessageBuffer * respToDir, network="To", virtual_network="2", - ordered="false", vnet_type="dmaresponse"; + vnet_type="dmaresponse"; { state_declaration(State, desc="DMA states", default="DMA_State_READY") { @@ -69,8 +69,8 @@ machine(DMA, "DMA Controller") bool isPresent(Address); } - MessageBuffer mandatoryQueue, ordered="false"; - MessageBuffer triggerQueue, ordered="true"; + MessageBuffer mandatoryQueue; + MessageBuffer triggerQueue; TBETable TBEs, template="", constructor="m_number_of_TBEs"; State cur_state; -- cgit v1.2.3