From 54d76f0ce5d721ad3b4de168db98054844e634cc Mon Sep 17 00:00:00 2001
From: Brad Beckmann <Brad.Beckmann@amd.com>
Date: Fri, 20 Aug 2010 11:46:12 -0700
Subject: ruby: Fixed L2 cache miss profiling

Fixed L2 cache miss profiling for the MOESI_CMP_token protocol
---
 src/mem/protocol/MOESI_CMP_token-L1cache.sm | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

(limited to 'src/mem/protocol/MOESI_CMP_token-L1cache.sm')

diff --git a/src/mem/protocol/MOESI_CMP_token-L1cache.sm b/src/mem/protocol/MOESI_CMP_token-L1cache.sm
index 381debce5..4af3338d8 100644
--- a/src/mem/protocol/MOESI_CMP_token-L1cache.sm
+++ b/src/mem/protocol/MOESI_CMP_token-L1cache.sm
@@ -1357,7 +1357,11 @@ machine(L1Cache, "Token protocol")
 
   action(uu_profileMiss, "\u", desc="Profile the demand miss") {
     peek(mandatoryQueue_in, CacheMsg) {
-      // profile_miss(in_msg, id);
+      if (L1DcacheMemory.isTagPresent(address)) {
+        L1DcacheMemory.profileMiss(in_msg);
+      } else {
+        L1IcacheMemory.profileMiss(in_msg);
+      }
     }
   }
 
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