From 7c39d5df7ea61a39ad1b9a3aa70d22f0e2943b21 Mon Sep 17 00:00:00 2001 From: Lena Olson Date: Tue, 18 Jun 2013 16:58:33 -0500 Subject: ruby: restrict Address to being a type and not a variable name Change all occurrances of Address as a variable name to instead use Addr. Address is an allowed name in slicc even when Address is also being used as a type, leading to declarations of "Address Address". While this works, it prevents adding another field of type Address because the compiler then thinks Address is a variable name, not type. Committed by: Nilay Vaish --- src/mem/protocol/MOESI_hammer-cache.sm | 104 ++++++++++++++++----------------- 1 file changed, 52 insertions(+), 52 deletions(-) (limited to 'src/mem/protocol/MOESI_hammer-cache.sm') diff --git a/src/mem/protocol/MOESI_hammer-cache.sm b/src/mem/protocol/MOESI_hammer-cache.sm index df14e690a..8ffa2c2ac 100644 --- a/src/mem/protocol/MOESI_hammer-cache.sm +++ b/src/mem/protocol/MOESI_hammer-cache.sm @@ -329,15 +329,15 @@ machine(L1Cache, "AMD Hammer-like protocol") if (triggerQueue_in.isReady()) { peek(triggerQueue_in, TriggerMsg) { - Entry cache_entry := getCacheEntry(in_msg.Address); - TBE tbe := TBEs[in_msg.Address]; + Entry cache_entry := getCacheEntry(in_msg.Addr); + TBE tbe := TBEs[in_msg.Addr]; if (in_msg.Type == TriggerType:L2_to_L1) { - trigger(Event:Complete_L2_to_L1, in_msg.Address, cache_entry, tbe); + trigger(Event:Complete_L2_to_L1, in_msg.Addr, cache_entry, tbe); } else if (in_msg.Type == TriggerType:ALL_ACKS) { - trigger(Event:All_acks, in_msg.Address, cache_entry, tbe); + trigger(Event:All_acks, in_msg.Addr, cache_entry, tbe); } else if (in_msg.Type == TriggerType:ALL_ACKS_NO_SHARERS) { - trigger(Event:All_acks_no_sharers, in_msg.Address, cache_entry, tbe); + trigger(Event:All_acks_no_sharers, in_msg.Addr, cache_entry, tbe); } else { error("Unexpected message"); } @@ -350,21 +350,21 @@ machine(L1Cache, "AMD Hammer-like protocol") // Response Network in_port(responseToCache_in, ResponseMsg, responseToCache, rank=2) { if (responseToCache_in.isReady()) { - peek(responseToCache_in, ResponseMsg, block_on="Address") { + peek(responseToCache_in, ResponseMsg, block_on="Addr") { - Entry cache_entry := getCacheEntry(in_msg.Address); - TBE tbe := TBEs[in_msg.Address]; + Entry cache_entry := getCacheEntry(in_msg.Addr); + TBE tbe := TBEs[in_msg.Addr]; if (in_msg.Type == CoherenceResponseType:ACK) { - trigger(Event:Ack, in_msg.Address, cache_entry, tbe); + trigger(Event:Ack, in_msg.Addr, cache_entry, tbe); } else if (in_msg.Type == CoherenceResponseType:ACK_SHARED) { - trigger(Event:Shared_Ack, in_msg.Address, cache_entry, tbe); + trigger(Event:Shared_Ack, in_msg.Addr, cache_entry, tbe); } else if (in_msg.Type == CoherenceResponseType:DATA) { - trigger(Event:Data, in_msg.Address, cache_entry, tbe); + trigger(Event:Data, in_msg.Addr, cache_entry, tbe); } else if (in_msg.Type == CoherenceResponseType:DATA_SHARED) { - trigger(Event:Shared_Data, in_msg.Address, cache_entry, tbe); + trigger(Event:Shared_Data, in_msg.Addr, cache_entry, tbe); } else if (in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE) { - trigger(Event:Exclusive_Data, in_msg.Address, cache_entry, tbe); + trigger(Event:Exclusive_Data, in_msg.Addr, cache_entry, tbe); } else { error("Unexpected message"); } @@ -375,38 +375,38 @@ machine(L1Cache, "AMD Hammer-like protocol") // Forward Network in_port(forwardToCache_in, RequestMsg, forwardToCache, rank=1) { if (forwardToCache_in.isReady()) { - peek(forwardToCache_in, RequestMsg, block_on="Address") { + peek(forwardToCache_in, RequestMsg, block_on="Addr") { - Entry cache_entry := getCacheEntry(in_msg.Address); - TBE tbe := TBEs[in_msg.Address]; + Entry cache_entry := getCacheEntry(in_msg.Addr); + TBE tbe := TBEs[in_msg.Addr]; if ((in_msg.Type == CoherenceRequestType:GETX) || (in_msg.Type == CoherenceRequestType:GETF)) { - trigger(Event:Other_GETX, in_msg.Address, cache_entry, tbe); + trigger(Event:Other_GETX, in_msg.Addr, cache_entry, tbe); } else if (in_msg.Type == CoherenceRequestType:MERGED_GETS) { - trigger(Event:Merged_GETS, in_msg.Address, cache_entry, tbe); + trigger(Event:Merged_GETS, in_msg.Addr, cache_entry, tbe); } else if (in_msg.Type == CoherenceRequestType:GETS) { if (machineCount(MachineType:L1Cache) > 1) { if (is_valid(cache_entry)) { if (IsAtomicAccessed(cache_entry) && no_mig_atomic) { - trigger(Event:Other_GETS_No_Mig, in_msg.Address, cache_entry, tbe); + trigger(Event:Other_GETS_No_Mig, in_msg.Addr, cache_entry, tbe); } else { - trigger(Event:Other_GETS, in_msg.Address, cache_entry, tbe); + trigger(Event:Other_GETS, in_msg.Addr, cache_entry, tbe); } } else { - trigger(Event:Other_GETS, in_msg.Address, cache_entry, tbe); + trigger(Event:Other_GETS, in_msg.Addr, cache_entry, tbe); } } else { - trigger(Event:NC_DMA_GETS, in_msg.Address, cache_entry, tbe); + trigger(Event:NC_DMA_GETS, in_msg.Addr, cache_entry, tbe); } } else if (in_msg.Type == CoherenceRequestType:INV) { - trigger(Event:Invalidate, in_msg.Address, cache_entry, tbe); + trigger(Event:Invalidate, in_msg.Addr, cache_entry, tbe); } else if (in_msg.Type == CoherenceRequestType:WB_ACK) { - trigger(Event:Writeback_Ack, in_msg.Address, cache_entry, tbe); + trigger(Event:Writeback_Ack, in_msg.Addr, cache_entry, tbe); } else if (in_msg.Type == CoherenceRequestType:WB_NACK) { - trigger(Event:Writeback_Nack, in_msg.Address, cache_entry, tbe); + trigger(Event:Writeback_Nack, in_msg.Addr, cache_entry, tbe); } else if (in_msg.Type == CoherenceRequestType:BLOCK_ACK) { - trigger(Event:Block_Ack, in_msg.Address, cache_entry, tbe); + trigger(Event:Block_Ack, in_msg.Addr, cache_entry, tbe); } else { error("Unexpected message"); } @@ -548,7 +548,7 @@ machine(L1Cache, "AMD Hammer-like protocol") action(a_issueGETS, "a", desc="Issue GETS") { enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) { assert(is_valid(tbe)); - out_msg.Address := address; + out_msg.Addr := address; out_msg.Type := CoherenceRequestType:GETS; out_msg.Requestor := machineID; out_msg.Destination.add(map_Address_to_Directory(address)); @@ -563,7 +563,7 @@ machine(L1Cache, "AMD Hammer-like protocol") action(b_issueGETX, "b", desc="Issue GETX") { enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) { assert(is_valid(tbe)); - out_msg.Address := address; + out_msg.Addr := address; out_msg.Type := CoherenceRequestType:GETX; out_msg.Requestor := machineID; out_msg.Destination.add(map_Address_to_Directory(address)); @@ -579,7 +579,7 @@ machine(L1Cache, "AMD Hammer-like protocol") if (machineCount(MachineType:L1Cache) > 1) { enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) { assert(is_valid(tbe)); - out_msg.Address := address; + out_msg.Addr := address; out_msg.Type := CoherenceRequestType:GETX; out_msg.Requestor := machineID; out_msg.Destination.add(map_Address_to_Directory(address)); @@ -595,7 +595,7 @@ machine(L1Cache, "AMD Hammer-like protocol") action(bf_issueGETF, "bf", desc="Issue GETF") { enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) { assert(is_valid(tbe)); - out_msg.Address := address; + out_msg.Addr := address; out_msg.Type := CoherenceRequestType:GETF; out_msg.Requestor := machineID; out_msg.Destination.add(map_Address_to_Directory(address)); @@ -611,7 +611,7 @@ machine(L1Cache, "AMD Hammer-like protocol") peek(forwardToCache_in, RequestMsg) { enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) { assert(is_valid(cache_entry)); - out_msg.Address := address; + out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE; out_msg.Sender := machineID; out_msg.Destination.add(in_msg.Requestor); @@ -634,7 +634,7 @@ machine(L1Cache, "AMD Hammer-like protocol") peek(forwardToCache_in, RequestMsg) { enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) { assert(is_valid(tbe)); - out_msg.Address := address; + out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE; out_msg.Sender := machineID; out_msg.Destination.add(in_msg.Requestor); @@ -655,7 +655,7 @@ machine(L1Cache, "AMD Hammer-like protocol") action(d_issuePUT, "d", desc="Issue PUT") { enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) { - out_msg.Address := address; + out_msg.Addr := address; out_msg.Type := CoherenceRequestType:PUT; out_msg.Requestor := machineID; out_msg.Destination.add(map_Address_to_Directory(address)); @@ -665,7 +665,7 @@ machine(L1Cache, "AMD Hammer-like protocol") action(df_issuePUTF, "df", desc="Issue PUTF") { enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) { - out_msg.Address := address; + out_msg.Addr := address; out_msg.Type := CoherenceRequestType:PUTF; out_msg.Requestor := machineID; out_msg.Destination.add(map_Address_to_Directory(address)); @@ -677,7 +677,7 @@ machine(L1Cache, "AMD Hammer-like protocol") peek(forwardToCache_in, RequestMsg) { enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) { assert(is_valid(cache_entry)); - out_msg.Address := address; + out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA; out_msg.Sender := machineID; out_msg.Destination.add(in_msg.Requestor); @@ -700,7 +700,7 @@ machine(L1Cache, "AMD Hammer-like protocol") peek(forwardToCache_in, RequestMsg) { enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) { assert(is_valid(cache_entry)); - out_msg.Address := address; + out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA_SHARED; out_msg.Sender := machineID; out_msg.Destination.add(in_msg.Requestor); @@ -724,7 +724,7 @@ machine(L1Cache, "AMD Hammer-like protocol") peek(forwardToCache_in, RequestMsg) { enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) { assert(is_valid(tbe)); - out_msg.Address := address; + out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA_SHARED; out_msg.Sender := machineID; out_msg.Destination.add(in_msg.Requestor); @@ -748,7 +748,7 @@ machine(L1Cache, "AMD Hammer-like protocol") peek(forwardToCache_in, RequestMsg) { enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) { assert(is_valid(cache_entry)); - out_msg.Address := address; + out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA_SHARED; out_msg.Sender := machineID; out_msg.Destination := in_msg.MergedRequestors; @@ -768,7 +768,7 @@ machine(L1Cache, "AMD Hammer-like protocol") peek(forwardToCache_in, RequestMsg) { enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) { assert(is_valid(tbe)); - out_msg.Address := address; + out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA_SHARED; out_msg.Sender := machineID; out_msg.Destination := in_msg.MergedRequestors; @@ -787,7 +787,7 @@ machine(L1Cache, "AMD Hammer-like protocol") action(f_sendAck, "f", desc="Send ack from cache to requestor") { peek(forwardToCache_in, RequestMsg) { enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) { - out_msg.Address := address; + out_msg.Addr := address; out_msg.Type := CoherenceResponseType:ACK; out_msg.Sender := machineID; out_msg.Destination.add(in_msg.Requestor); @@ -804,7 +804,7 @@ machine(L1Cache, "AMD Hammer-like protocol") action(ff_sendAckShared, "\f", desc="Send shared ack from cache to requestor") { peek(forwardToCache_in, RequestMsg) { enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) { - out_msg.Address := address; + out_msg.Addr := address; out_msg.Type := CoherenceResponseType:ACK_SHARED; out_msg.Sender := machineID; out_msg.Destination.add(in_msg.Requestor); @@ -820,7 +820,7 @@ machine(L1Cache, "AMD Hammer-like protocol") action(g_sendUnblock, "g", desc="Send unblock to memory") { enqueue(unblockNetwork_out, ResponseMsg, latency=cache_response_latency) { - out_msg.Address := address; + out_msg.Addr := address; out_msg.Type := CoherenceResponseType:UNBLOCK; out_msg.Sender := machineID; out_msg.Destination.add(map_Address_to_Directory(address)); @@ -830,7 +830,7 @@ machine(L1Cache, "AMD Hammer-like protocol") action(gm_sendUnblockM, "gm", desc="Send unblock to memory and indicate M/O/E state") { enqueue(unblockNetwork_out, ResponseMsg, latency=cache_response_latency) { - out_msg.Address := address; + out_msg.Addr := address; out_msg.Type := CoherenceResponseType:UNBLOCKM; out_msg.Sender := machineID; out_msg.Destination.add(map_Address_to_Directory(address)); @@ -841,7 +841,7 @@ machine(L1Cache, "AMD Hammer-like protocol") action(gs_sendUnblockS, "gs", desc="Send unblock to memory and indicate S state") { enqueue(unblockNetwork_out, ResponseMsg, latency=cache_response_latency) { assert(is_valid(tbe)); - out_msg.Address := address; + out_msg.Addr := address; out_msg.Type := CoherenceResponseType:UNBLOCKS; out_msg.Sender := machineID; out_msg.CurOwner := tbe.CurOwner; @@ -864,7 +864,7 @@ machine(L1Cache, "AMD Hammer-like protocol") peek(responseToCache_in, ResponseMsg) { sequencer.readCallback(address, - getNondirectHitMachType(in_msg.Address, in_msg.Sender), + getNondirectHitMachType(in_msg.Addr, in_msg.Sender), cache_entry.DataBlk, tbe.InitialRequestTime, tbe.ForwardRequestTime, @@ -1015,7 +1015,7 @@ machine(L1Cache, "AMD Hammer-like protocol") action(ll_L2toL1Transfer, "ll", desc="") { enqueue(triggerQueue_out, TriggerMsg, latency=l2_cache_hit_latency) { - out_msg.Address := address; + out_msg.Addr := address; out_msg.Type := TriggerType:L2_to_L1; } } @@ -1024,7 +1024,7 @@ machine(L1Cache, "AMD Hammer-like protocol") assert(is_valid(tbe)); if (tbe.NumPendingMsgs == 0) { enqueue(triggerQueue_out, TriggerMsg) { - out_msg.Address := address; + out_msg.Addr := address; if (tbe.Sharers) { out_msg.Type := TriggerType:ALL_ACKS; } else { @@ -1049,7 +1049,7 @@ machine(L1Cache, "AMD Hammer-like protocol") assert(in_msg.Requestor != machineID); enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) { assert(is_valid(tbe)); - out_msg.Address := address; + out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA; out_msg.Sender := machineID; out_msg.Destination.add(in_msg.Requestor); @@ -1074,7 +1074,7 @@ machine(L1Cache, "AMD Hammer-like protocol") assert(in_msg.Requestor != machineID); enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) { assert(is_valid(tbe)); - out_msg.Address := address; + out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA_SHARED; out_msg.Sender := machineID; out_msg.Destination.add(in_msg.Requestor); @@ -1098,7 +1098,7 @@ machine(L1Cache, "AMD Hammer-like protocol") peek(forwardToCache_in, RequestMsg) { enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) { assert(is_valid(tbe)); - out_msg.Address := address; + out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA_SHARED; out_msg.Sender := machineID; out_msg.Destination := in_msg.MergedRequestors; @@ -1117,7 +1117,7 @@ machine(L1Cache, "AMD Hammer-like protocol") action(qq_sendDataFromTBEToMemory, "\q", desc="Send data from TBE to memory") { enqueue(unblockNetwork_out, ResponseMsg, latency=cache_response_latency) { assert(is_valid(tbe)); - out_msg.Address := address; + out_msg.Addr := address; out_msg.Sender := machineID; out_msg.Destination.add(map_Address_to_Directory(address)); out_msg.Dirty := tbe.Dirty; @@ -1148,7 +1148,7 @@ machine(L1Cache, "AMD Hammer-like protocol") action(t_sendExclusiveDataFromTBEToMemory, "t", desc="Send exclusive data from TBE to memory") { enqueue(unblockNetwork_out, ResponseMsg, latency=cache_response_latency) { assert(is_valid(tbe)); - out_msg.Address := address; + out_msg.Addr := address; out_msg.Sender := machineID; out_msg.Destination.add(map_Address_to_Directory(address)); out_msg.DataBlk := tbe.DataBlk; -- cgit v1.2.3