From 1764ebbf30cfd94eb7ccc618ade0d70049db000e Mon Sep 17 00:00:00 2001 From: Nilay Vaish Date: Tue, 22 Mar 2011 06:41:54 -0500 Subject: Ruby: Remove CacheMsg class from SLICC The goal of the patch is to do away with the CacheMsg class currently in use in coherence protocols. In place of CacheMsg, the RubyRequest class will used. This class is already present in slicc_interface/RubyRequest.hh. In fact, objects of class CacheMsg are generated by copying values from a RubyRequest object. --- src/mem/protocol/RubySlicc_Exports.sm | 11 ----------- 1 file changed, 11 deletions(-) (limited to 'src/mem/protocol/RubySlicc_Exports.sm') diff --git a/src/mem/protocol/RubySlicc_Exports.sm b/src/mem/protocol/RubySlicc_Exports.sm index 1f7a1dda2..0ef3df29b 100644 --- a/src/mem/protocol/RubySlicc_Exports.sm +++ b/src/mem/protocol/RubySlicc_Exports.sm @@ -213,17 +213,6 @@ enumeration(PrefetchBit, default="PrefetchBit_No", desc="...") { L2_HW, desc="This is a L2 hardware prefetch"; } -// CacheMsg -structure(CacheMsg, desc="...", interface="Message") { - Address LineAddress, desc="Line address for this request"; - Address PhysicalAddress, desc="Physical address for this request"; - RubyRequestType Type, desc="Type of request (LD, ST, etc)"; - Address ProgramCounter, desc="Program counter of the instruction that caused the miss"; - RubyAccessMode AccessMode, desc="user/supervisor access type"; - int Size, desc="size in bytes of access"; - PrefetchBit Prefetch, desc="Is this a prefetch request"; -} - // CacheMsg structure(SequencerMsg, desc="...", interface="Message") { Address LineAddress, desc="Line address for this request"; -- cgit v1.2.3