From 54d76f0ce5d721ad3b4de168db98054844e634cc Mon Sep 17 00:00:00 2001
From: Brad Beckmann <Brad.Beckmann@amd.com>
Date: Fri, 20 Aug 2010 11:46:12 -0700
Subject: ruby: Fixed L2 cache miss profiling

Fixed L2 cache miss profiling for the MOESI_CMP_token protocol
---
 src/mem/protocol/RubySlicc_Types.sm | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'src/mem/protocol/RubySlicc_Types.sm')

diff --git a/src/mem/protocol/RubySlicc_Types.sm b/src/mem/protocol/RubySlicc_Types.sm
index 7fc817600..8dcdabeb8 100644
--- a/src/mem/protocol/RubySlicc_Types.sm
+++ b/src/mem/protocol/RubySlicc_Types.sm
@@ -126,6 +126,11 @@ external_type(CacheMemory) {
   void changePermission(Address, AccessPermission);
   bool isTagPresent(Address);
   void profileMiss(CacheMsg);
+
+  void profileGenericRequest(GenericRequestType,
+                             AccessModeType,
+                             PrefetchBit);
+
   void setMRU(Address);
 }
 
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