From 74ca89f8b7d9b340d1d4f83511b57a2dfa2a70df Mon Sep 17 00:00:00 2001
From: David Hashe <david.hashe@amd.com>
Date: Mon, 20 Jul 2015 09:15:18 -0500
Subject: ruby: give access to cache tag/data latencies from SLICC

This patch exposes the tag and data array latencies to the SLICC state machines
so that it can be used to determine the correct enqueue latency for response
messages.
---
 src/mem/protocol/RubySlicc_Types.sm | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/mem/protocol/RubySlicc_Types.sm')

diff --git a/src/mem/protocol/RubySlicc_Types.sm b/src/mem/protocol/RubySlicc_Types.sm
index fb506781c..88b9839bb 100644
--- a/src/mem/protocol/RubySlicc_Types.sm
+++ b/src/mem/protocol/RubySlicc_Types.sm
@@ -149,6 +149,8 @@ structure (CacheMemory, external = "yes") {
   void deallocate(Address);
   AbstractCacheEntry lookup(Address);
   bool isTagPresent(Address);
+  Cycles getTagLatency();
+  Cycles getDataLatency();
   void setMRU(Address);
   void recordRequestType(CacheRequestType);
   bool checkResourceAvailable(CacheResourceType, Address);
-- 
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