From 143d8ea698a832d80afb1a0cd6726cee1d47d4b5 Mon Sep 17 00:00:00 2001 From: Brad Beckmann Date: Fri, 29 Jan 2010 20:29:34 -0800 Subject: ruby: removed last level cache support Removed the last level cache support and MOESI_hammer's dependency on it. Replaces the LLC support with the more generic MachineType count. --- src/mem/protocol/MOESI_hammer-cache.sm | 4 ++-- src/mem/protocol/MOESI_hammer-dir.sm | 4 ++-- src/mem/protocol/RubySlicc_ComponentMapping.sm | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) (limited to 'src/mem/protocol') diff --git a/src/mem/protocol/MOESI_hammer-cache.sm b/src/mem/protocol/MOESI_hammer-cache.sm index 66bb85cf9..4bdfcb23d 100644 --- a/src/mem/protocol/MOESI_hammer-cache.sm +++ b/src/mem/protocol/MOESI_hammer-cache.sm @@ -379,7 +379,7 @@ machine(L1Cache, "AMD Hammer-like protocol") out_msg.Requestor := machineID; out_msg.Destination.add(map_Address_to_Directory(address)); out_msg.MessageSize := MessageSizeType:Request_Control; - TBEs[address].NumPendingMsgs := getNumberOfLastLevelCaches(); // One from each other cache (n-1) plus the memory (+1) + TBEs[address].NumPendingMsgs := machineCount(MachineType:L1Cache); // One from each other cache (n-1) plus the memory (+1) } } @@ -390,7 +390,7 @@ machine(L1Cache, "AMD Hammer-like protocol") out_msg.Requestor := machineID; out_msg.Destination.add(map_Address_to_Directory(address)); out_msg.MessageSize := MessageSizeType:Request_Control; - TBEs[address].NumPendingMsgs := getNumberOfLastLevelCaches(); // One from each other cache (n-1) plus the memory (+1) + TBEs[address].NumPendingMsgs := machineCount(MachineType:L1Cache); // One from each other cache (n-1) plus the memory (+1) } } diff --git a/src/mem/protocol/MOESI_hammer-dir.sm b/src/mem/protocol/MOESI_hammer-dir.sm index 57433dd3d..3cbeb8431 100644 --- a/src/mem/protocol/MOESI_hammer-dir.sm +++ b/src/mem/protocol/MOESI_hammer-dir.sm @@ -320,7 +320,7 @@ machine(Directory, "AMD Hammer-like protocol") // // One ack for each last-level cache // - TBEs[address].NumPendingMsgs := getNumberOfLastLevelCaches(); + TBEs[address].NumPendingMsgs := machineCount(MachineType:L1Cache); // // Assume initially that the caches store a clean copy and that memory // will provide the data @@ -468,7 +468,7 @@ machine(Directory, "AMD Hammer-like protocol") } action(f_forwardRequest, "f", desc="Forward requests") { - if (getNumberOfLastLevelCaches() > 1) { + if (machineCount(MachineType:L1Cache) > 1) { peek(requestQueue_in, RequestMsg) { enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) { out_msg.Address := address; diff --git a/src/mem/protocol/RubySlicc_ComponentMapping.sm b/src/mem/protocol/RubySlicc_ComponentMapping.sm index 891820c46..3c777e965 100644 --- a/src/mem/protocol/RubySlicc_ComponentMapping.sm +++ b/src/mem/protocol/RubySlicc_ComponentMapping.sm @@ -29,7 +29,7 @@ // Mapping functions -int getNumberOfLastLevelCaches(); +int machineCount(MachineType machType); // NodeID map_address_to_node(Address addr); MachineID mapAddressToRange(Address addr, MachineType type, int low, int high); -- cgit v1.2.3