From 95735e10e7ea85320ee39c15a4132eece8417af4 Mon Sep 17 00:00:00 2001 From: "Mitch Hayenga ext:(%2C%20Amin%20Farmahini%20%3Caminfar%40gmail.com%3E)" Date: Wed, 29 Jan 2014 23:21:25 -0600 Subject: mem: prefetcher: add options, support for unaligned addresses This patch extends the classic prefetcher to work on non-block aligned addresses. Because the existing prefetchers in gem5 mask off the lower address bits of cache accesses, many predictable strides fail to be detected. For example, if a load were to stride by 48 bytes, with 64 byte cachelines, the current stride based prefetcher would see an access pattern of 0, 64, 64, 128, 192.... Thus not detecting a constant stride pattern. This patch fixes this, by training the prefetcher on access and not masking off the lower address bits. It also adds the following configuration options: 1) Training/prefetching only on cache misses, 2) Training/prefetching only on data acceses, 3) Optionally tagging prefetches with a PC address. #3 allows prefetchers to train off of prefetch requests in systems with multiple cache levels and PC-based prefetchers present at multiple levels. It also effectively allows a pipelining of prefetch requests (like in POWER4) across multiple levels of cache hierarchy. Improves performance on my gem5 configuration by 4.3% for SPECINT and 4.7% for SPECFP (geomean). --- src/mem/request.hh | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'src/mem/request.hh') diff --git a/src/mem/request.hh b/src/mem/request.hh index 28d378628..e84a77272 100644 --- a/src/mem/request.hh +++ b/src/mem/request.hh @@ -576,6 +576,13 @@ class Request return _threadId; } + void + setPC(Addr pc) + { + privateFlags.set(VALID_PC); + _pc = pc; + } + bool hasPC() const { -- cgit v1.2.3