From 2f30950143cc70bc42a3c8a4111d7cf8198ec881 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Mon, 11 May 2009 10:38:43 -0700 Subject: ruby: Import ruby and slicc from GEMS We eventually plan to replace the m5 cache hierarchy with the GEMS hierarchy, but for now we will make both live alongside eachother. --- src/mem/ruby/network/simple/Switch.cc | 205 ++++++++++++++++++++++++++++++++++ 1 file changed, 205 insertions(+) create mode 100644 src/mem/ruby/network/simple/Switch.cc (limited to 'src/mem/ruby/network/simple/Switch.cc') diff --git a/src/mem/ruby/network/simple/Switch.cc b/src/mem/ruby/network/simple/Switch.cc new file mode 100644 index 000000000..3b55d156f --- /dev/null +++ b/src/mem/ruby/network/simple/Switch.cc @@ -0,0 +1,205 @@ + +/* + * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Switch.C + * + * Description: See Switch.h + * + * $Id$ + * + */ + + +#include "Switch.hh" +#include "PerfectSwitch.hh" +#include "MessageBuffer.hh" +#include "Throttle.hh" +#include "MessageSizeType.hh" +#include "Network.hh" +#include "Protocol.hh" + +Switch::Switch(SwitchID sid, SimpleNetwork* network_ptr) +{ + m_perfect_switch_ptr = new PerfectSwitch(sid, network_ptr); + m_switch_id = sid; + m_throttles.setSize(0); +} + +Switch::~Switch() +{ + delete m_perfect_switch_ptr; + + // Delete throttles (one per output port) + m_throttles.deletePointers(); + + // Delete MessageBuffers + m_buffers_to_free.deletePointers(); +} + +void Switch::addInPort(const Vector& in) +{ + m_perfect_switch_ptr->addInPort(in); +} + +void Switch::addOutPort(const Vector& out, const NetDest& routing_table_entry, int link_latency, int bw_multiplier) +{ + Throttle* throttle_ptr = NULL; + + // Create a throttle + throttle_ptr = new Throttle(m_switch_id, m_throttles.size(), link_latency, bw_multiplier); + m_throttles.insertAtBottom(throttle_ptr); + + // Create one buffer per vnet (these are intermediaryQueues) + Vector intermediateBuffers; + for (int i=0; isetOrdering(true); + if(FINITE_BUFFERING) { + buffer_ptr->setSize(FINITE_BUFFER_SIZE); + } + intermediateBuffers.insertAtBottom(buffer_ptr); + m_buffers_to_free.insertAtBottom(buffer_ptr); + } + + // Hook the queues to the PerfectSwitch + m_perfect_switch_ptr->addOutPort(intermediateBuffers, routing_table_entry); + + // Hook the queues to the Throttle + throttle_ptr->addLinks(intermediateBuffers, out); + +} + +void Switch::clearRoutingTables() +{ + m_perfect_switch_ptr->clearRoutingTables(); +} + +void Switch::clearBuffers() +{ + m_perfect_switch_ptr->clearBuffers(); + for (int i=0; iclear(); + } + } +} + +void Switch::reconfigureOutPort(const NetDest& routing_table_entry) +{ + m_perfect_switch_ptr->reconfigureOutPort(routing_table_entry); +} + +const Throttle* Switch::getThrottle(LinkID link_number) const +{ + assert(m_throttles[link_number] != NULL); + return m_throttles[link_number]; +} + +const Vector* Switch::getThrottles() const +{ + return &m_throttles; +} + +void Switch::printStats(ostream& out) const +{ + out << "switch_" << m_switch_id << "_inlinks: " << m_perfect_switch_ptr->getInLinks() << endl; + out << "switch_" << m_switch_id << "_outlinks: " << m_perfect_switch_ptr->getOutLinks() << endl; + + // Average link utilizations + double average_utilization = 0.0; + int throttle_count = 0; + + for (int i=0; igetUtilization(); + throttle_count++; + } + } + average_utilization = (throttle_count == 0) ? 0 : average_utilization / float(throttle_count); + + // Individual link utilizations + out << "links_utilized_percent_switch_" << m_switch_id << ": " << average_utilization << endl; + for (int link=0; linkgetUtilization() << " bw: " << throttle_ptr->getLinkBandwidth() + << " base_latency: " << throttle_ptr->getLatency() << endl; + } + } + out << endl; + + // Traffic breakdown + for (int link=0; link >& message_counts = throttle_ptr->getCounters(); + for (int int_type=0; int_typegetLatency() << endl; + } + } + } + } + out << endl; +} + +void Switch::clearStats() +{ + m_perfect_switch_ptr->clearStats(); + for (int i=0; iclearStats(); + } + } +} + +void Switch::printConfig(ostream& out) const +{ + m_perfect_switch_ptr->printConfig(out); + for (int i=0; iprintConfig(out); + } + } +} + +void Switch::print(ostream& out) const +{ + // FIXME printing + out << "[Switch]"; +} + -- cgit v1.2.3