From beb6e57c6f6141ad959bb97b49daad7f1fa54af3 Mon Sep 17 00:00:00 2001 From: Nilay Vaish Date: Tue, 25 Jun 2013 00:32:03 -0500 Subject: ruby: profiler: lots of inter-related changes The patch started of with removing the global variables from the profiler for profiling the miss latency of requests made to the cache. The corrresponding histograms have been moved to the Sequencer. These are combined together when the histograms are printed. Separate histograms are now maintained for tracking latency of all requests together, of hits only and of misses only. A particular set of histograms used to use the type GenericMachineType defined in one of the protocol files. This patch removes this type. Now, everything that relied on this type would use MachineType instead. To do this, SLICC has been changed so that multiple machine types can be declared by a controller in its preamble. --- src/mem/ruby/profiler/Profiler.hh | 37 +------------------------------------ 1 file changed, 1 insertion(+), 36 deletions(-) (limited to 'src/mem/ruby/profiler/Profiler.hh') diff --git a/src/mem/ruby/profiler/Profiler.hh b/src/mem/ruby/profiler/Profiler.hh index 23efed67a..e7b3c5f8d 100644 --- a/src/mem/ruby/profiler/Profiler.hh +++ b/src/mem/ruby/profiler/Profiler.hh @@ -52,7 +52,6 @@ #include "base/hashmap.hh" #include "mem/protocol/AccessType.hh" -#include "mem/protocol/GenericMachineType.hh" #include "mem/protocol/PrefetchBit.hh" #include "mem/protocol/RubyAccessMode.hh" #include "mem/protocol/RubyRequestType.hh" @@ -110,21 +109,7 @@ class Profiler : public SimObject void controllerBusy(MachineID machID); void bankBusy(); - - void missLatency(Cycles t, RubyRequestType type, - const GenericMachineType respondingMach); - - void missLatencyWcc(Cycles issuedTime, Cycles initialRequestTime, - Cycles forwardRequestTime, Cycles firstResponseTime, - Cycles completionTime); - - void missLatencyDir(Cycles issuedTime, Cycles initialRequestTime, - Cycles forwardRequestTime, Cycles firstResponseTime, - Cycles completionTime); - void swPrefetchLatency(Cycles t, RubyRequestType type, - const GenericMachineType respondingMach); - void print(std::ostream& out) const; void rubyWatch(int proc); @@ -141,6 +126,7 @@ class Profiler : public SimObject void printRequestProfile(std::ostream &out) const; void printDelayProfile(std::ostream &out) const; void printOutstandingReqProfile(std::ostream &out) const; + void printMissLatencyProfile(std::ostream &out) const; private: // Private copy constructor and assignment operator @@ -161,27 +147,6 @@ class Profiler : public SimObject int64 m_cache_to_cache; int64 m_memory_to_cache; - std::vector m_missLatencyHistograms; - std::vector m_machLatencyHistograms; - std::vector< std::vector > m_missMachLatencyHistograms; - Histogram m_wCCIssueToInitialRequestHistogram; - Histogram m_wCCInitialRequestToForwardRequestHistogram; - Histogram m_wCCForwardRequestToFirstResponseHistogram; - Histogram m_wCCFirstResponseToCompleteHistogram; - int64 m_wCCIncompleteTimes; - Histogram m_dirIssueToInitialRequestHistogram; - Histogram m_dirInitialRequestToForwardRequestHistogram; - Histogram m_dirForwardRequestToFirstResponseHistogram; - Histogram m_dirFirstResponseToCompleteHistogram; - int64 m_dirIncompleteTimes; - - Histogram m_allMissLatencyHistogram; - - Histogram m_allSWPrefetchLatencyHistogram; - Histogram m_SWPrefetchL2MissLatencyHistogram; - std::vector m_SWPrefetchLatencyHistograms; - std::vector m_SWPrefetchMachLatencyHistograms; - Histogram m_average_latency_estimate; m5::hash_set
m_watch_address_set; -- cgit v1.2.3