From 407f37e15f19a2da350a94272ac7739891e935f4 Mon Sep 17 00:00:00 2001 From: Nilay Vaish Date: Fri, 10 Jan 2014 16:19:47 -0600 Subject: ruby: move all statistics to stats.txt, eliminate ruby.stats --- src/mem/ruby/profiler/AddressProfiler.hh | 2 + src/mem/ruby/profiler/Profiler.cc | 577 ++++++++++--------------------- src/mem/ruby/profiler/Profiler.hh | 113 +++--- src/mem/ruby/profiler/Profiler.py | 40 --- src/mem/ruby/profiler/SConscript | 2 - 5 files changed, 231 insertions(+), 503 deletions(-) delete mode 100644 src/mem/ruby/profiler/Profiler.py (limited to 'src/mem/ruby/profiler') diff --git a/src/mem/ruby/profiler/AddressProfiler.hh b/src/mem/ruby/profiler/AddressProfiler.hh index 642b5a41a..9bf1d517d 100644 --- a/src/mem/ruby/profiler/AddressProfiler.hh +++ b/src/mem/ruby/profiler/AddressProfiler.hh @@ -67,6 +67,8 @@ class AddressProfiler //added by SS void setHotLines(bool hot_lines); void setAllInstructions(bool all_instructions); + void regStats(const std::string &name) {} + void collateStats() {} private: // Private copy constructor and assignment operator diff --git a/src/mem/ruby/profiler/Profiler.cc b/src/mem/ruby/profiler/Profiler.cc index d0ea7921c..6f7da1eda 100644 --- a/src/mem/ruby/profiler/Profiler.cc +++ b/src/mem/ruby/profiler/Profiler.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood + * Copyright (c) 1999-2013 Mark D. Hill and David A. Wood * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -61,32 +61,21 @@ using namespace std; using m5::stl_helpers::operator<<; -Profiler::Profiler(const Params *p) - : SimObject(p) +Profiler::Profiler(const RubySystemParams *p) + : m_IncompleteTimes(MachineType_NUM) { - m_inst_profiler_ptr = NULL; - m_address_profiler_ptr = NULL; - m_real_time_start_time = time(NULL); // Not reset in clearStats() - m_hot_lines = p->hot_lines; m_all_instructions = p->all_instructions; - m_num_of_sequencers = p->num_of_sequencers; - - m_hot_lines = false; - m_all_instructions = false; - - m_address_profiler_ptr = new AddressProfiler(m_num_of_sequencers); + m_address_profiler_ptr = new AddressProfiler(p->num_of_sequencers); m_address_profiler_ptr->setHotLines(m_hot_lines); m_address_profiler_ptr->setAllInstructions(m_all_instructions); if (m_all_instructions) { - m_inst_profiler_ptr = new AddressProfiler(m_num_of_sequencers); + m_inst_profiler_ptr = new AddressProfiler(p->num_of_sequencers); m_inst_profiler_ptr->setHotLines(m_hot_lines); m_inst_profiler_ptr->setAllInstructions(m_all_instructions); } - - p->ruby_system->registerProfiler(this); } Profiler::~Profiler() @@ -94,74 +83,176 @@ Profiler::~Profiler() } void -Profiler::print(ostream& out) const +Profiler::regStats(const std::string &pName) { - out << "[Profiler]"; -} - -void -Profiler::printRequestProfile(ostream &out) const -{ - out << "Request vs. RubySystem State Profile" << endl; - out << "--------------------------------" << endl; - out << endl; + if (!m_all_instructions) { + m_address_profiler_ptr->regStats(pName); + } - map m_requestProfileMap; - uint64_t m_requests = 0; + if (m_all_instructions) { + m_inst_profiler_ptr->regStats(pName); + } - for (uint32_t i = 0; i < MachineType_NUM; i++) { - for (map::iterator it = - g_abs_controls[i].begin(); - it != g_abs_controls[i].end(); ++it) { + delayHistogram + .init(10) + .name(pName + ".delayHist") + .desc("delay histogram for all message") + .flags(Stats::nozero | Stats::pdf | Stats::oneline); - AbstractController *ctr = (*it).second; - map mp = ctr->getRequestProfileMap(); + uint32_t numVNets = Network::getNumberOfVirtualNetworks(); + for (int i = 0; i < numVNets; i++) { + delayVCHistogram.push_back(new Stats::Histogram()); + delayVCHistogram[i] + ->init(10) + .name(pName + csprintf(".delayVCHist.vnet_%i", i)) + .desc(csprintf("delay histogram for vnet_%i", i)) + .flags(Stats::nozero | Stats::pdf | Stats::oneline); + } - for (map::iterator jt = mp.begin(); - jt != mp.end(); ++jt) { + m_outstandReqHist + .init(10) + .name(pName + ".outstanding_req_hist") + .desc("") + .flags(Stats::nozero | Stats::pdf | Stats::oneline); + + m_latencyHist + .init(10) + .name(pName + ".latency_hist") + .desc("") + .flags(Stats::nozero | Stats::pdf | Stats::oneline); + + m_hitLatencyHist + .init(10) + .name(pName + ".hit_latency_hist") + .desc("") + .flags(Stats::nozero | Stats::pdf | Stats::oneline); + + m_missLatencyHist + .init(10) + .name(pName + ".miss_latency_hist") + .desc("") + .flags(Stats::nozero | Stats::pdf | Stats::oneline); - map::iterator kt = - m_requestProfileMap.find((*jt).first); - if (kt != m_requestProfileMap.end()) { - (*kt).second += (*jt).second; - } else { - m_requestProfileMap[(*jt).first] = (*jt).second; - } - } + for (int i = 0; i < RubyRequestType_NUM; i++) { + m_typeLatencyHist.push_back(new Stats::Histogram()); + m_typeLatencyHist[i] + ->init(10) + .name(pName + csprintf(".%s.latency_hist", + RubyRequestType(i))) + .desc("") + .flags(Stats::nozero | Stats::pdf | Stats::oneline); + + m_hitTypeLatencyHist.push_back(new Stats::Histogram()); + m_hitTypeLatencyHist[i] + ->init(10) + .name(pName + csprintf(".%s.hit_latency_hist", + RubyRequestType(i))) + .desc("") + .flags(Stats::nozero | Stats::pdf | Stats::oneline); + + m_missTypeLatencyHist.push_back(new Stats::Histogram()); + m_missTypeLatencyHist[i] + ->init(10) + .name(pName + csprintf(".%s.miss_latency_hist", + RubyRequestType(i))) + .desc("") + .flags(Stats::nozero | Stats::pdf | Stats::oneline); + } - m_requests += ctr->getRequestCount(); - } + for (int i = 0; i < MachineType_NUM; i++) { + m_hitMachLatencyHist.push_back(new Stats::Histogram()); + m_hitMachLatencyHist[i] + ->init(10) + .name(pName + csprintf(".%s.hit_mach_latency_hist", + MachineType(i))) + .desc("") + .flags(Stats::nozero | Stats::pdf | Stats::oneline); + + m_missMachLatencyHist.push_back(new Stats::Histogram()); + m_missMachLatencyHist[i] + ->init(10) + .name(pName + csprintf(".%s.miss_mach_latency_hist", + MachineType(i))) + .desc("") + .flags(Stats::nozero | Stats::pdf | Stats::oneline); + + m_IssueToInitialDelayHist.push_back(new Stats::Histogram()); + m_IssueToInitialDelayHist[i] + ->init(10) + .name(pName + csprintf( + ".%s.miss_latency_hist.issue_to_initial_request", + MachineType(i))) + .desc("") + .flags(Stats::nozero | Stats::pdf | Stats::oneline); + + m_InitialToForwardDelayHist.push_back(new Stats::Histogram()); + m_InitialToForwardDelayHist[i] + ->init(10) + .name(pName + csprintf(".%s.miss_latency_hist.initial_to_forward", + MachineType(i))) + .desc("") + .flags(Stats::nozero | Stats::pdf | Stats::oneline); + + m_ForwardToFirstResponseDelayHist.push_back(new Stats::Histogram()); + m_ForwardToFirstResponseDelayHist[i] + ->init(10) + .name(pName + csprintf( + ".%s.miss_latency_hist.forward_to_first_response", + MachineType(i))) + .desc("") + .flags(Stats::nozero | Stats::pdf | Stats::oneline); + + m_FirstResponseToCompletionDelayHist.push_back(new Stats::Histogram()); + m_FirstResponseToCompletionDelayHist[i] + ->init(10) + .name(pName + csprintf( + ".%s.miss_latency_hist.first_response_to_completion", + MachineType(i))) + .desc("") + .flags(Stats::nozero | Stats::pdf | Stats::oneline); + + m_IncompleteTimes[i] + .name(pName + csprintf(".%s.incomplete_times", MachineType(i))) + .desc("") + .flags(Stats::nozero); } - map::const_iterator i = m_requestProfileMap.begin(); - map::const_iterator end = m_requestProfileMap.end(); - for (; i != end; ++i) { - const string &key = i->first; - uint64_t count = i->second; - - double percent = (100.0 * double(count)) / double(m_requests); - vector items; - tokenize(items, key, ':'); - vector::iterator j = items.begin(); - vector::iterator end = items.end(); - for (; j != end; ++i) - out << setw(10) << *j; - out << setw(11) << count; - out << setw(14) << percent << endl; + for (int i = 0; i < RubyRequestType_NUM; i++) { + m_hitTypeMachLatencyHist.push_back(std::vector()); + m_missTypeMachLatencyHist.push_back(std::vector()); + + for (int j = 0; j < MachineType_NUM; j++) { + m_hitTypeMachLatencyHist[i].push_back(new Stats::Histogram()); + m_hitTypeMachLatencyHist[i][j] + ->init(10) + .name(pName + csprintf(".%s.%s.hit_type_mach_latency_hist", + RubyRequestType(i), MachineType(j))) + .desc("") + .flags(Stats::nozero | Stats::pdf | Stats::oneline); + + m_missTypeMachLatencyHist[i].push_back(new Stats::Histogram()); + m_missTypeMachLatencyHist[i][j] + ->init(10) + .name(pName + csprintf(".%s.%s.miss_type_mach_latency_hist", + RubyRequestType(i), MachineType(j))) + .desc("") + .flags(Stats::nozero | Stats::pdf | Stats::oneline); + } } - out << endl; } void -Profiler::printDelayProfile(ostream &out) const +Profiler::collateStats() { - out << "Message Delayed Cycles" << endl; - out << "----------------------" << endl; + if (!m_all_instructions) { + m_address_profiler_ptr->collateStats(); + } - uint32_t numVNets = Network::getNumberOfVirtualNetworks(); - Histogram delayHistogram; - std::vector delayVCHistogram(numVNets); + if (m_all_instructions) { + m_inst_profiler_ptr->collateStats(); + } + uint32_t numVNets = Network::getNumberOfVirtualNetworks(); for (uint32_t i = 0; i < MachineType_NUM; i++) { for (map::iterator it = g_abs_controls[i].begin(); @@ -171,314 +262,81 @@ Profiler::printDelayProfile(ostream &out) const delayHistogram.add(ctr->getDelayHist()); for (uint32_t i = 0; i < numVNets; i++) { - delayVCHistogram[i].add(ctr->getDelayVCHist(i)); + delayVCHistogram[i]->add(ctr->getDelayVCHist(i)); } } } - out << "Total_delay_cycles: " << delayHistogram << endl; - - for (int i = 0; i < numVNets; i++) { - out << " virtual_network_" << i << "_delay_cycles: " - << delayVCHistogram[i] << endl; - } -} - -void -Profiler::printOutstandingReqProfile(ostream &out) const -{ - Histogram sequencerRequests; - for (uint32_t i = 0; i < MachineType_NUM; i++) { for (map::iterator it = - g_abs_controls[i].begin(); - it != g_abs_controls[i].end(); ++it) { + g_abs_controls[i].begin(); + it != g_abs_controls[i].end(); ++it) { AbstractController *ctr = (*it).second; Sequencer *seq = ctr->getSequencer(); if (seq != NULL) { - sequencerRequests.add(seq->getOutstandReqHist()); + m_outstandReqHist.add(seq->getOutstandReqHist()); } } } - out << "sequencer_requests_outstanding: " - << sequencerRequests << endl; -} - -void -Profiler::printMissLatencyProfile(ostream &out) const -{ - // Collate the miss latencies histograms from all the sequencers - Histogram latency_hist; - std::vector type_latency_hist(RubyRequestType_NUM); - - Histogram hit_latency_hist; - std::vector hit_type_latency_hist(RubyRequestType_NUM); - - std::vector hit_mach_latency_hist(MachineType_NUM); - std::vector > - hit_type_mach_latency_hist(RubyRequestType_NUM, - std::vector(MachineType_NUM)); - - Histogram miss_latency_hist; - std::vector miss_type_latency_hist(RubyRequestType_NUM); - - std::vector miss_mach_latency_hist(MachineType_NUM); - std::vector > - miss_type_mach_latency_hist(RubyRequestType_NUM, - std::vector(MachineType_NUM)); - - std::vector issue_to_initial_delay_hist(MachineType_NUM); - std::vector initial_to_forward_delay_hist(MachineType_NUM); - std::vector - forward_to_first_response_delay_hist(MachineType_NUM); - std::vector - first_response_to_completion_delay_hist(MachineType_NUM); - std::vector incomplete_times(MachineType_NUM); - for (uint32_t i = 0; i < MachineType_NUM; i++) { for (map::iterator it = - g_abs_controls[i].begin(); - it != g_abs_controls[i].end(); ++it) { + g_abs_controls[i].begin(); + it != g_abs_controls[i].end(); ++it) { AbstractController *ctr = (*it).second; Sequencer *seq = ctr->getSequencer(); if (seq != NULL) { // add all the latencies - latency_hist.add(seq->getLatencyHist()); - hit_latency_hist.add(seq->getHitLatencyHist()); - miss_latency_hist.add(seq->getMissLatencyHist()); + m_latencyHist.add(seq->getLatencyHist()); + m_hitLatencyHist.add(seq->getHitLatencyHist()); + m_missLatencyHist.add(seq->getMissLatencyHist()); // add the per request type latencies for (uint32_t j = 0; j < RubyRequestType_NUM; ++j) { - type_latency_hist[j] - .add(seq->getTypeLatencyHist(j)); - hit_type_latency_hist[j] - .add(seq->getHitTypeLatencyHist(j)); - miss_type_latency_hist[j] - .add(seq->getMissTypeLatencyHist(j)); + m_typeLatencyHist[j] + ->add(seq->getTypeLatencyHist(j)); + m_hitTypeLatencyHist[j] + ->add(seq->getHitTypeLatencyHist(j)); + m_missTypeLatencyHist[j] + ->add(seq->getMissTypeLatencyHist(j)); } // add the per machine type miss latencies for (uint32_t j = 0; j < MachineType_NUM; ++j) { - hit_mach_latency_hist[j] - .add(seq->getHitMachLatencyHist(j)); - miss_mach_latency_hist[j] - .add(seq->getMissMachLatencyHist(j)); + m_hitMachLatencyHist[j] + ->add(seq->getHitMachLatencyHist(j)); + m_missMachLatencyHist[j] + ->add(seq->getMissMachLatencyHist(j)); - issue_to_initial_delay_hist[j].add( + m_IssueToInitialDelayHist[j]->add( seq->getIssueToInitialDelayHist(MachineType(j))); - initial_to_forward_delay_hist[j].add( + m_InitialToForwardDelayHist[j]->add( seq->getInitialToForwardDelayHist(MachineType(j))); - forward_to_first_response_delay_hist[j].add(seq-> + m_ForwardToFirstResponseDelayHist[j]->add(seq-> getForwardRequestToFirstResponseHist(MachineType(j))); - first_response_to_completion_delay_hist[j].add(seq-> - getFirstResponseToCompletionDelayHist(MachineType(j))); - incomplete_times[j] += + m_FirstResponseToCompletionDelayHist[j]->add(seq-> + getFirstResponseToCompletionDelayHist( + MachineType(j))); + m_IncompleteTimes[j] += seq->getIncompleteTimes(MachineType(j)); } // add the per (request, machine) type miss latencies for (uint32_t j = 0; j < RubyRequestType_NUM; j++) { for (uint32_t k = 0; k < MachineType_NUM; k++) { - hit_type_mach_latency_hist[j][k].add( - seq->getHitTypeMachLatencyHist(j,k)); - miss_type_mach_latency_hist[j][k].add( - seq->getMissTypeMachLatencyHist(j,k)); + m_hitTypeMachLatencyHist[j][k]->add( + seq->getHitTypeMachLatencyHist(j,k)); + m_missTypeMachLatencyHist[j][k]->add( + seq->getMissTypeMachLatencyHist(j,k)); } } } } } - - out << "latency: " << latency_hist << endl; - for (int i = 0; i < RubyRequestType_NUM; i++) { - if (type_latency_hist[i].size() > 0) { - out << "latency: " << RubyRequestType(i) << ": " - << type_latency_hist[i] << endl; - } - } - - out << "hit latency: " << hit_latency_hist << endl; - for (int i = 0; i < RubyRequestType_NUM; i++) { - if (hit_type_latency_hist[i].size() > 0) { - out << "hit latency: " << RubyRequestType(i) << ": " - << hit_type_latency_hist[i] << endl; - } - } - - for (int i = 0; i < MachineType_NUM; i++) { - if (hit_mach_latency_hist[i].size() > 0) { - out << "hit latency: " << MachineType(i) << ": " - << hit_mach_latency_hist[i] << endl; - } - } - - for (int i = 0; i < RubyRequestType_NUM; i++) { - for (int j = 0; j < MachineType_NUM; j++) { - if (hit_type_mach_latency_hist[i][j].size() > 0) { - out << "hit latency: " << RubyRequestType(i) - << ": " << MachineType(j) << ": " - << hit_type_mach_latency_hist[i][j] << endl; - } - } - } - - out << "miss latency: " << miss_latency_hist << endl; - for (int i = 0; i < RubyRequestType_NUM; i++) { - if (miss_type_latency_hist[i].size() > 0) { - out << "miss latency: " << RubyRequestType(i) << ": " - << miss_type_latency_hist[i] << endl; - } - } - - for (int i = 0; i < MachineType_NUM; i++) { - if (miss_mach_latency_hist[i].size() > 0) { - out << "miss latency: " << MachineType(i) << ": " - << miss_mach_latency_hist[i] << endl; - - out << "miss latency: " << MachineType(i) - << "::issue_to_initial_request: " - << issue_to_initial_delay_hist[i] << endl; - out << "miss latency: " << MachineType(i) - << "::initial_to_forward_request: " - << initial_to_forward_delay_hist[i] << endl; - out << "miss latency: " << MachineType(i) - << "::forward_to_first_response: " - << forward_to_first_response_delay_hist[i] << endl; - out << "miss latency: " << MachineType(i) - << "::first_response_to_completion: " - << first_response_to_completion_delay_hist[i] << endl; - out << "incomplete times: " << incomplete_times[i] << endl; - } - } - - for (int i = 0; i < RubyRequestType_NUM; i++) { - for (int j = 0; j < MachineType_NUM; j++) { - if (miss_type_mach_latency_hist[i][j].size() > 0) { - out << "miss latency: " << RubyRequestType(i) - << ": " << MachineType(j) << ": " - << miss_type_mach_latency_hist[i][j] << endl; - } - } - } - - out << endl; -} - -void -Profiler::printStats(ostream& out, bool short_stats) -{ - out << endl; - if (short_stats) { - out << "SHORT "; - } - out << "Profiler Stats" << endl; - out << "--------------" << endl; - - Cycles ruby_cycles = g_system_ptr->curCycle()-m_ruby_start; - - out << "Ruby_current_time: " << g_system_ptr->curCycle() << endl; - out << "Ruby_start_time: " << m_ruby_start << endl; - out << "Ruby_cycles: " << ruby_cycles << endl; - out << endl; - - if (!short_stats) { - out << "Busy Controller Counts:" << endl; - for (uint32_t i = 0; i < MachineType_NUM; i++) { - uint32_t size = MachineType_base_count((MachineType)i); - - for (uint32_t j = 0; j < size; j++) { - MachineID machID; - machID.type = (MachineType)i; - machID.num = j; - - AbstractController *ctr = - (*(g_abs_controls[i].find(j))).second; - out << machID << ":" << ctr->getFullyBusyCycles() << " "; - if ((j + 1) % 8 == 0) { - out << endl; - } - } - out << endl; - } - out << endl; - - out << "Busy Bank Count:" << m_busyBankCount << endl; - out << endl; - - printOutstandingReqProfile(out); - out << endl; - } - - if (!short_stats) { - out << "All Non-Zero Cycle Demand Cache Accesses" << endl; - out << "----------------------------------------" << endl; - printMissLatencyProfile(out); - - if (m_all_sharing_histogram.size() > 0) { - out << "all_sharing: " << m_all_sharing_histogram << endl; - out << "read_sharing: " << m_read_sharing_histogram << endl; - out << "write_sharing: " << m_write_sharing_histogram << endl; - - out << "all_sharing_percent: "; - m_all_sharing_histogram.printPercent(out); - out << endl; - - out << "read_sharing_percent: "; - m_read_sharing_histogram.printPercent(out); - out << endl; - - out << "write_sharing_percent: "; - m_write_sharing_histogram.printPercent(out); - out << endl; - - int64 total_miss = m_cache_to_cache + m_memory_to_cache; - out << "all_misses: " << total_miss << endl; - out << "cache_to_cache_misses: " << m_cache_to_cache << endl; - out << "memory_to_cache_misses: " << m_memory_to_cache << endl; - out << "cache_to_cache_percent: " - << 100.0 * (double(m_cache_to_cache) / double(total_miss)) - << endl; - out << "memory_to_cache_percent: " - << 100.0 * (double(m_memory_to_cache) / double(total_miss)) - << endl; - out << endl; - } - - printRequestProfile(out); - - if (!m_all_instructions) { - m_address_profiler_ptr->printStats(out); - } - - if (m_all_instructions) { - m_inst_profiler_ptr->printStats(out); - } - - out << endl; - printDelayProfile(out); - } -} - -void -Profiler::clearStats() -{ - m_ruby_start = g_system_ptr->curCycle(); - m_real_time_start_time = time(NULL); - - m_busyBankCount = 0; - m_read_sharing_histogram.clear(); - m_write_sharing_histogram.clear(); - m_all_sharing_histogram.clear(); - m_cache_to_cache = 0; - m_memory_to_cache = 0; - - // update the start time - m_ruby_start = g_system_ptr->curCycle(); } void @@ -496,60 +354,3 @@ Profiler::addAddressTraceSample(const RubyRequest& msg, NodeID id) msg.getType(), msg.getAccessMode(), id, false); } } - -void -Profiler::profileSharing(const Address& addr, AccessType type, - NodeID requestor, const Set& sharers, - const Set& owner) -{ - Set set_contacted(owner); - if (type == AccessType_Write) { - set_contacted.addSet(sharers); - } - set_contacted.remove(requestor); - int number_contacted = set_contacted.count(); - - if (type == AccessType_Write) { - m_write_sharing_histogram.add(number_contacted); - } else { - m_read_sharing_histogram.add(number_contacted); - } - m_all_sharing_histogram.add(number_contacted); - - if (number_contacted == 0) { - m_memory_to_cache++; - } else { - m_cache_to_cache++; - } -} - -void -Profiler::bankBusy() -{ - m_busyBankCount++; -} - -void -Profiler::rubyWatch(int id) -{ - uint64 tr = 0; - Address watch_address = Address(tr); - - DPRINTFN("%7s %3s RUBY WATCH %d\n", g_system_ptr->curCycle(), id, - watch_address); - - // don't care about success or failure - m_watch_address_set.insert(watch_address); -} - -bool -Profiler::watchAddress(Address addr) -{ - return m_watch_address_set.count(addr) > 0; -} - -Profiler * -RubyProfilerParams::create() -{ - return new Profiler(this); -} diff --git a/src/mem/ruby/profiler/Profiler.hh b/src/mem/ruby/profiler/Profiler.hh index e7b3c5f8d..247c705b0 100644 --- a/src/mem/ruby/profiler/Profiler.hh +++ b/src/mem/ruby/profiler/Profiler.hh @@ -45,89 +45,43 @@ #ifndef __MEM_RUBY_PROFILER_PROFILER_HH__ #define __MEM_RUBY_PROFILER_PROFILER_HH__ -#include #include #include #include +#include "base/callback.hh" #include "base/hashmap.hh" +#include "base/statistics.hh" #include "mem/protocol/AccessType.hh" #include "mem/protocol/PrefetchBit.hh" #include "mem/protocol/RubyAccessMode.hh" #include "mem/protocol/RubyRequestType.hh" -#include "mem/ruby/common/Address.hh" #include "mem/ruby/common/Global.hh" -#include "mem/ruby/common/Histogram.hh" -#include "mem/ruby/common/Set.hh" #include "mem/ruby/system/MachineID.hh" -#include "mem/ruby/system/MemoryControl.hh" -#include "params/RubyProfiler.hh" -#include "sim/sim_object.hh" +#include "params/RubySystem.hh" class RubyRequest; class AddressProfiler; -class Profiler : public SimObject +class Profiler { public: - typedef RubyProfilerParams Params; - Profiler(const Params *); + Profiler(const RubySystemParams *); ~Profiler(); void wakeup(); - - void setPeriodicStatsFile(const std::string& filename); - void setPeriodicStatsInterval(int64_t period); - - void printStats(std::ostream& out, bool short_stats=false); - void printShortStats(std::ostream& out) { printStats(out, true); } - void printTraceStats(std::ostream& out) const; - void clearStats(); - void printResourceUsage(std::ostream& out) const; + void regStats(const std::string &name); + void collateStats(); AddressProfiler* getAddressProfiler() { return m_address_profiler_ptr; } AddressProfiler* getInstructionProfiler() { return m_inst_profiler_ptr; } void addAddressTraceSample(const RubyRequest& msg, NodeID id); - void profileRequest(const std::string& requestStr); - void profileSharing(const Address& addr, AccessType type, - NodeID requestor, const Set& sharers, - const Set& owner); - - void profileMulticastRetry(const Address& addr, int count); - - void profileFilterAction(int action); - - void profileConflictingRequests(const Address& addr); - - void - profileAverageLatencyEstimate(int latency) - { - m_average_latency_estimate.add(latency); - } - - void controllerBusy(MachineID machID); - void bankBusy(); - - void print(std::ostream& out) const; - - void rubyWatch(int proc); - bool watchAddress(Address addr); - - // return Ruby's start time - Cycles getRubyStartTime() { return m_ruby_start; } - // added by SS bool getHotLines() { return m_hot_lines; } bool getAllInstructions() { return m_all_instructions; } - private: - void printRequestProfile(std::ostream &out) const; - void printDelayProfile(std::ostream &out) const; - void printOutstandingReqProfile(std::ostream &out) const; - void printMissLatencyProfile(std::ostream &out) const; - private: // Private copy constructor and assignment operator Profiler(const Profiler& obj); @@ -136,33 +90,46 @@ class Profiler : public SimObject AddressProfiler* m_address_profiler_ptr; AddressProfiler* m_inst_profiler_ptr; - Cycles m_ruby_start; - time_t m_real_time_start_time; + Stats::Histogram delayHistogram; + std::vector delayVCHistogram; + + //! Histogram for number of outstanding requests per cycle. + Stats::Histogram m_outstandReqHist; + + //! Histogram for holding latency profile of all requests. + Stats::Histogram m_latencyHist; + std::vector m_typeLatencyHist; + + //! Histogram for holding latency profile of all requests that + //! hit in the controller connected to this sequencer. + Stats::Histogram m_hitLatencyHist; + std::vector m_hitTypeLatencyHist; - int64_t m_busyBankCount; + //! Histograms for profiling the latencies for requests that + //! did not required external messages. + std::vector m_hitMachLatencyHist; + std::vector< std::vector > m_hitTypeMachLatencyHist; - Histogram m_read_sharing_histogram; - Histogram m_write_sharing_histogram; - Histogram m_all_sharing_histogram; - int64 m_cache_to_cache; - int64 m_memory_to_cache; + //! Histogram for holding latency profile of all requests that + //! miss in the controller connected to this sequencer. + Stats::Histogram m_missLatencyHist; + std::vector m_missTypeLatencyHist; - Histogram m_average_latency_estimate; - m5::hash_set
m_watch_address_set; + //! Histograms for profiling the latencies for requests that + //! required external messages. + std::vector m_missMachLatencyHist; + std::vector< std::vector > m_missTypeMachLatencyHist; + + //! Histograms for recording the breakdown of miss latency + std::vector m_IssueToInitialDelayHist; + std::vector m_InitialToForwardDelayHist; + std::vector m_ForwardToFirstResponseDelayHist; + std::vector m_FirstResponseToCompletionDelayHist; + std::vector m_IncompleteTimes; //added by SS bool m_hot_lines; bool m_all_instructions; - - int m_num_of_sequencers; }; -inline std::ostream& -operator<<(std::ostream& out, const Profiler& obj) -{ - obj.print(out); - out << std::flush; - return out; -} - #endif // __MEM_RUBY_PROFILER_PROFILER_HH__ diff --git a/src/mem/ruby/profiler/Profiler.py b/src/mem/ruby/profiler/Profiler.py deleted file mode 100644 index 0bb1bbc3d..000000000 --- a/src/mem/ruby/profiler/Profiler.py +++ /dev/null @@ -1,40 +0,0 @@ -# Copyright (c) 2009 Advanced Micro Devices, Inc. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer; -# redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution; -# neither the name of the copyright holders nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Steve Reinhardt -# Brad Beckmann - -from m5.params import * -from m5.SimObject import SimObject - -class RubyProfiler(SimObject): - type = 'RubyProfiler' - cxx_class = 'Profiler' - cxx_header = "mem/ruby/profiler/Profiler.hh" - hot_lines = Param.Bool(False, "") - all_instructions = Param.Bool(False, "") - num_of_sequencers = Param.Int("") - ruby_system = Param.RubySystem("") diff --git a/src/mem/ruby/profiler/SConscript b/src/mem/ruby/profiler/SConscript index 613c70aa0..d1e9972e4 100644 --- a/src/mem/ruby/profiler/SConscript +++ b/src/mem/ruby/profiler/SConscript @@ -33,8 +33,6 @@ Import('*') if env['PROTOCOL'] == 'None': Return() -SimObject('Profiler.py') - Source('AccessTraceForAddress.cc') Source('AddressProfiler.cc') Source('MemCntrlProfiler.cc') -- cgit v1.2.3