From 496d5ed3e1f7dad42b0c2ebe0050d84621be8f99 Mon Sep 17 00:00:00 2001 From: Tiago Muck Date: Tue, 19 Feb 2019 15:58:33 -0600 Subject: mem-ruby: Hit latencies defined by the controllers Removed the icache/dcache hit latency parameters from the Sequencer. They were replaced by the mandatory queue enqueue latency that is now defined by the top-level cache controller. By default, the latency is defined by the mandatory_queue_latency parameter. When the latency depends on specific protocol states or on the request type, the protocol may override the mandatoryQueueLatency function. Change-Id: I72e57a7ea49501ef81dc7f591bef14134274647c Signed-off-by: Tiago Muck Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18413 Tested-by: kokoro Reviewed-by: Nikos Nikoleris Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power --- src/mem/ruby/slicc_interface/AbstractController.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/mem/ruby/slicc_interface/AbstractController.cc') diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc b/src/mem/ruby/slicc_interface/AbstractController.cc index 68edcba59..c953e8257 100644 --- a/src/mem/ruby/slicc_interface/AbstractController.cc +++ b/src/mem/ruby/slicc_interface/AbstractController.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017 ARM Limited + * Copyright (c) 2017,2019 ARM Limited * All rights reserved. * * The license below extends only to copyright in the software and shall @@ -55,6 +55,7 @@ AbstractController::AbstractController(const Params *p) m_number_of_TBEs(p->number_of_TBEs), m_transitions_per_cycle(p->transitions_per_cycle), m_buffer_size(p->buffer_size), m_recycle_latency(p->recycle_latency), + m_mandatory_queue_latency(p->mandatory_queue_latency), memoryPort(csprintf("%s.memory", name()), this, ""), addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()) { -- cgit v1.2.3