From d3d24835bcc03ecf312ac6ba7df114656770730f Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Thu, 7 Mar 2019 03:02:35 -0800 Subject: arch, cpu, dev, gpu, mem, sim, python: start using getPort. Replace the getMasterPort, getSlavePort, and getEthPort functions with getPort, and remove extraneous mechanisms that are no longer necessary. Change-Id: Iab7e3c02d2f3a0cf33e7e824e18c28646b5bc318 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17040 Reviewed-by: Daniel Carvalho Reviewed-by: Andreas Sandberg Maintainer: Andreas Sandberg --- src/mem/ruby/slicc_interface/AbstractController.hh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mem/ruby/slicc_interface/AbstractController.hh') diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh b/src/mem/ruby/slicc_interface/AbstractController.hh index 35cd3d2a5..5e39a28d2 100644 --- a/src/mem/ruby/slicc_interface/AbstractController.hh +++ b/src/mem/ruby/slicc_interface/AbstractController.hh @@ -126,8 +126,8 @@ class AbstractController : public MemObject, public Consumer virtual void initNetQueues() = 0; /** A function used to return the port associated with this bus object. */ - BaseMasterPort& getMasterPort(const std::string& if_name, - PortID idx = InvalidPortID); + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID); void queueMemoryRead(const MachineID &id, Addr addr, Cycles latency); void queueMemoryWrite(const MachineID &id, Addr addr, Cycles latency, -- cgit v1.2.3