From 8f29298bc7a9aee1572ba3de66ed12db5995509c Mon Sep 17 00:00:00 2001 From: Nilay Vaish Date: Sat, 5 Sep 2015 09:35:31 -0500 Subject: ruby: adds set and way indices to AbstractCacheEntry --- src/mem/ruby/slicc_interface/AbstractCacheEntry.hh | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) (limited to 'src/mem/ruby/slicc_interface') diff --git a/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh b/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh index 2b318957f..926556781 100644 --- a/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh +++ b/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh @@ -62,9 +62,22 @@ class AbstractCacheEntry : public AbstractEntry void clearLocked(); bool isLocked(int context) const; - Addr m_Address; // Address of this block, required by CacheMemory - int m_locked; // Holds info whether the address is locked, - // required for implementing LL/SC + void setSetIndex(uint32_t s) { m_set_index = s; } + uint32_t getSetIndex() const { return m_set_index; } + + void setWayIndex(uint32_t s) { m_way_index = s; } + uint32_t getWayIndex() const { return m_way_index; } + + // Address of this block, required by CacheMemory + Addr m_Address; + // Holds info whether the address is locked. + // Required for implementing LL/SC operations. + int m_locked; + + private: + // Set and way coordinates of the entry within the cache memory object. + uint32_t m_set_index; + uint32_t m_way_index; }; inline std::ostream& -- cgit v1.2.3