From fc3d34a4889f96395d7d3185a0c5a2dbb5c77343 Mon Sep 17 00:00:00 2001
From: Nilay Vaish <nilay@cs.wisc.edu>
Date: Thu, 27 Aug 2015 12:51:40 -0500
Subject: ruby: handle llsc accesses through CacheEntry, not CacheMemory

The sequencer takes care of llsc accesses by calling upon functions
from the CacheMemory.  This is unnecessary once the required CacheEntry object
is available.  Thus some of the calls to findTagInSet() are avoided.
---
 src/mem/ruby/slicc_interface/AbstractCacheEntry.cc | 25 ++++++++++++++++++++++
 src/mem/ruby/slicc_interface/AbstractCacheEntry.hh |  5 +++++
 2 files changed, 30 insertions(+)

(limited to 'src/mem/ruby/slicc_interface')

diff --git a/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc b/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
index 01fd3f522..416aea73b 100644
--- a/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
+++ b/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
@@ -28,6 +28,9 @@
 
 #include "mem/ruby/slicc_interface/AbstractCacheEntry.hh"
 
+#include "base/trace.hh"
+#include "debug/RubyCache.hh"
+
 AbstractCacheEntry::AbstractCacheEntry()
 {
     m_Permission = AccessPermission_NotPresent;
@@ -48,3 +51,25 @@ AbstractCacheEntry::changePermission(AccessPermission new_perm)
         m_locked = -1;
     }
 }
+
+void
+AbstractCacheEntry::setLocked(int context)
+{
+    DPRINTF(RubyCache, "Setting Lock for addr: %x to %d\n", m_Address, context);
+    m_locked = context;
+}
+
+void
+AbstractCacheEntry::clearLocked()
+{
+    DPRINTF(RubyCache, "Clear Lock for addr: %x\n", m_Address);
+    m_locked = -1;
+}
+
+bool
+AbstractCacheEntry::isLocked(int context) const
+{
+    DPRINTF(RubyCache, "Testing Lock for addr: %llx cur %d con %d\n",
+            m_Address, m_locked, context);
+    return m_locked == context;
+}
diff --git a/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh b/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
index 6c7a4a008..2b318957f 100644
--- a/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
+++ b/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
@@ -56,6 +56,11 @@ class AbstractCacheEntry : public AbstractEntry
     virtual DataBlock& getDataBlk()
     { panic("getDataBlk() not implemented!"); }
 
+    // Functions for locking and unlocking the cache entry.  These are required
+    // for supporting atomic memory accesses.
+    void setLocked(int context);
+    void clearLocked();
+    bool isLocked(int context) const;
 
     Addr m_Address; // Address of this block, required by CacheMemory
     int m_locked; // Holds info whether the address is locked,
-- 
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