From df973abef3a70074971375cfe52c46f53528c00e Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Thu, 16 Oct 2014 05:49:43 -0400 Subject: mem: Dynamically determine page bytes in memory components This patch takes a step towards an ISA-agnostic memory system by enabling the components to establish the page size after instantiation. The swap operation in the memory is now also allowing any granularity to avoid depending on the IntReg of the ISA. --- src/mem/ruby/structures/RubyPrefetcher.py | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/mem/ruby/structures/RubyPrefetcher.py') diff --git a/src/mem/ruby/structures/RubyPrefetcher.py b/src/mem/ruby/structures/RubyPrefetcher.py index a02b11696..18bb3dc69 100644 --- a/src/mem/ruby/structures/RubyPrefetcher.py +++ b/src/mem/ruby/structures/RubyPrefetcher.py @@ -27,7 +27,9 @@ # Authors: Nilay Vaish from m5.SimObject import SimObject +from System import System from m5.params import * +from m5.proxy import * class Prefetcher(SimObject): type = 'Prefetcher' @@ -45,3 +47,4 @@ class Prefetcher(SimObject): num_startup_pfs = Param.UInt32(1, "") cross_page = Param.Bool(False, """True if prefetched address can be on a page different from the observed address""") + sys = Param.System(Parent.any, "System this prefetcher belongs to") -- cgit v1.2.3