From 4727fc26f885d09f07f18a10fabe6c75dffe165f Mon Sep 17 00:00:00 2001 From: Nilay Vaish Date: Sat, 29 Aug 2015 10:19:23 -0500 Subject: ruby: eliminate type uint64 and int64 These types are being replaced with uint64_t and int64_t. --- .../ruby/structures/AbstractReplacementPolicy.cc | 2 +- .../ruby/structures/AbstractReplacementPolicy.hh | 6 +-- src/mem/ruby/structures/BankedArray.cc | 6 +-- src/mem/ruby/structures/BankedArray.hh | 8 ++-- src/mem/ruby/structures/CacheMemory.cc | 45 +++++++++++----------- src/mem/ruby/structures/CacheMemory.hh | 10 ++--- src/mem/ruby/structures/LRUPolicy.cc | 10 ++--- src/mem/ruby/structures/LRUPolicy.hh | 4 +- src/mem/ruby/structures/PseudoLRUPolicy.cc | 12 +++--- src/mem/ruby/structures/PseudoLRUPolicy.hh | 6 +-- src/mem/ruby/structures/RubyMemoryControl.cc | 6 +-- src/mem/ruby/structures/RubyMemoryControl.hh | 12 +++--- 12 files changed, 62 insertions(+), 65 deletions(-) (limited to 'src/mem/ruby/structures') diff --git a/src/mem/ruby/structures/AbstractReplacementPolicy.cc b/src/mem/ruby/structures/AbstractReplacementPolicy.cc index fbcce6e2d..d802ecd31 100644 --- a/src/mem/ruby/structures/AbstractReplacementPolicy.cc +++ b/src/mem/ruby/structures/AbstractReplacementPolicy.cc @@ -66,7 +66,7 @@ AbstractReplacementPolicy::~AbstractReplacementPolicy() } Tick -AbstractReplacementPolicy::getLastAccess(int64 set, int64 way) +AbstractReplacementPolicy::getLastAccess(int64_t set, int64_t way) { return m_last_ref_ptr[set][way]; } diff --git a/src/mem/ruby/structures/AbstractReplacementPolicy.hh b/src/mem/ruby/structures/AbstractReplacementPolicy.hh index 03ef0d2fd..c118f3c11 100644 --- a/src/mem/ruby/structures/AbstractReplacementPolicy.hh +++ b/src/mem/ruby/structures/AbstractReplacementPolicy.hh @@ -44,13 +44,13 @@ class AbstractReplacementPolicy : public SimObject virtual ~AbstractReplacementPolicy(); /* touch a block. a.k.a. update timestamp */ - virtual void touch(int64 set, int64 way, Tick time) = 0; + virtual void touch(int64_t set, int64_t way, Tick time) = 0; /* returns the way to replace */ - virtual int64 getVictim(int64 set) const = 0; + virtual int64_t getVictim(int64_t set) const = 0; /* get the time of the last access */ - Tick getLastAccess(int64 set, int64 way); + Tick getLastAccess(int64_t set, int64_t way); virtual bool useOccupancy() const { return false; } diff --git a/src/mem/ruby/structures/BankedArray.cc b/src/mem/ruby/structures/BankedArray.cc index 8bc3cf584..b25962df6 100644 --- a/src/mem/ruby/structures/BankedArray.cc +++ b/src/mem/ruby/structures/BankedArray.cc @@ -49,7 +49,7 @@ BankedArray::BankedArray(unsigned int banks, Cycles accessLatency, } bool -BankedArray::tryAccess(int64 idx) +BankedArray::tryAccess(int64_t idx) { if (accessLatency == 0) return true; @@ -65,7 +65,7 @@ BankedArray::tryAccess(int64 idx) } void -BankedArray::reserve(int64 idx) +BankedArray::reserve(int64_t idx) { if (accessLatency == 0) return; @@ -91,7 +91,7 @@ BankedArray::reserve(int64 idx) } unsigned int -BankedArray::mapIndexToBank(int64 idx) +BankedArray::mapIndexToBank(int64_t idx) { if (banks == 1) { return 0; diff --git a/src/mem/ruby/structures/BankedArray.hh b/src/mem/ruby/structures/BankedArray.hh index 438186944..179676f19 100644 --- a/src/mem/ruby/structures/BankedArray.hh +++ b/src/mem/ruby/structures/BankedArray.hh @@ -51,7 +51,7 @@ class BankedArray { public: AccessRecord() : idx(0), startAccess(0), endAccess(0) {} - int64 idx; + int64_t idx; Tick startAccess; Tick endAccess; }; @@ -60,7 +60,7 @@ class BankedArray // otherwise, schedule the event and wait for it to complete std::vector busyBanks; - unsigned int mapIndexToBank(int64 idx); + unsigned int mapIndexToBank(int64_t idx); public: BankedArray(unsigned int banks, Cycles accessLatency, @@ -68,9 +68,9 @@ class BankedArray // Note: We try the access based on the cache index, not the address // This is so we don't get aliasing on blocks being replaced - bool tryAccess(int64 idx); + bool tryAccess(int64_t idx); - void reserve(int64 idx); + void reserve(int64_t idx); Cycles getLatency() const { return accessLatency; } }; diff --git a/src/mem/ruby/structures/CacheMemory.cc b/src/mem/ruby/structures/CacheMemory.cc index bb26ff03c..17c13502d 100644 --- a/src/mem/ruby/structures/CacheMemory.cc +++ b/src/mem/ruby/structures/CacheMemory.cc @@ -98,7 +98,7 @@ CacheMemory::~CacheMemory() } // convert a Address to its location in the cache -int64 +int64_t CacheMemory::addressToCacheSet(Addr address) const { assert(address == makeLineAddress(address)); @@ -109,7 +109,7 @@ CacheMemory::addressToCacheSet(Addr address) const // Given a cache index: returns the index of the tag in a set. // returns -1 if the tag is not found. int -CacheMemory::findTagInSet(int64 cacheSet, Addr tag) const +CacheMemory::findTagInSet(int64_t cacheSet, Addr tag) const { assert(tag == makeLineAddress(tag)); // search the set for the tags @@ -124,7 +124,7 @@ CacheMemory::findTagInSet(int64 cacheSet, Addr tag) const // Given a cache index: returns the index of the tag in a set. // returns -1 if the tag is not found. int -CacheMemory::findTagInSetIgnorePermissions(int64 cacheSet, +CacheMemory::findTagInSetIgnorePermissions(int64_t cacheSet, Addr tag) const { assert(tag == makeLineAddress(tag)); @@ -164,7 +164,7 @@ CacheMemory::tryCacheAccess(Addr address, RubyRequestType type, { assert(address == makeLineAddress(address)); DPRINTF(RubyCache, "address: %s\n", address); - int64 cacheSet = addressToCacheSet(address); + int64_t cacheSet = addressToCacheSet(address); int loc = findTagInSet(cacheSet, address); if (loc != -1) { // Do we even have a tag match? @@ -191,7 +191,7 @@ CacheMemory::testCacheAccess(Addr address, RubyRequestType type, { assert(address == makeLineAddress(address)); DPRINTF(RubyCache, "address: %s\n", address); - int64 cacheSet = addressToCacheSet(address); + int64_t cacheSet = addressToCacheSet(address); int loc = findTagInSet(cacheSet, address); if (loc != -1) { @@ -213,7 +213,7 @@ bool CacheMemory::isTagPresent(Addr address) const { assert(address == makeLineAddress(address)); - int64 cacheSet = addressToCacheSet(address); + int64_t cacheSet = addressToCacheSet(address); int loc = findTagInSet(cacheSet, address); if (loc == -1) { @@ -233,7 +233,7 @@ CacheMemory::cacheAvail(Addr address) const { assert(address == makeLineAddress(address)); - int64 cacheSet = addressToCacheSet(address); + int64_t cacheSet = addressToCacheSet(address); for (int i = 0; i < m_cache_assoc; i++) { AbstractCacheEntry* entry = m_cache[cacheSet][i]; @@ -259,7 +259,7 @@ CacheMemory::allocate(Addr address, AbstractCacheEntry* entry, bool touch) DPRINTF(RubyCache, "address: %s\n", address); // Find the first open slot - int64 cacheSet = addressToCacheSet(address); + int64_t cacheSet = addressToCacheSet(address); std::vector &set = m_cache[cacheSet]; for (int i = 0; i < m_cache_assoc; i++) { if (!set[i] || set[i]->m_Permission == AccessPermission_NotPresent) { @@ -287,7 +287,7 @@ CacheMemory::deallocate(Addr address) assert(address == makeLineAddress(address)); assert(isTagPresent(address)); DPRINTF(RubyCache, "address: %s\n", address); - int64 cacheSet = addressToCacheSet(address); + int64_t cacheSet = addressToCacheSet(address); int loc = findTagInSet(cacheSet, address); if (loc != -1) { delete m_cache[cacheSet][loc]; @@ -303,7 +303,7 @@ CacheMemory::cacheProbe(Addr address) const assert(address == makeLineAddress(address)); assert(!cacheAvail(address)); - int64 cacheSet = addressToCacheSet(address); + int64_t cacheSet = addressToCacheSet(address); return m_cache[cacheSet][m_replacementPolicy_ptr->getVictim(cacheSet)]-> m_Address; } @@ -313,7 +313,7 @@ AbstractCacheEntry* CacheMemory::lookup(Addr address) { assert(address == makeLineAddress(address)); - int64 cacheSet = addressToCacheSet(address); + int64_t cacheSet = addressToCacheSet(address); int loc = findTagInSet(cacheSet, address); if(loc == -1) return NULL; return m_cache[cacheSet][loc]; @@ -324,7 +324,7 @@ const AbstractCacheEntry* CacheMemory::lookup(Addr address) const { assert(address == makeLineAddress(address)); - int64 cacheSet = addressToCacheSet(address); + int64_t cacheSet = addressToCacheSet(address); int loc = findTagInSet(cacheSet, address); if(loc == -1) return NULL; return m_cache[cacheSet][loc]; @@ -334,7 +334,7 @@ CacheMemory::lookup(Addr address) const void CacheMemory::setMRU(Addr address) { - int64 cacheSet = addressToCacheSet(address); + int64_t cacheSet = addressToCacheSet(address); int loc = findTagInSet(cacheSet, address); if(loc != -1) @@ -344,9 +344,9 @@ CacheMemory::setMRU(Addr address) void CacheMemory::recordCacheContents(int cntrl, CacheRecorder* tr) const { - uint64 warmedUpBlocks = 0; - uint64 totalBlocks M5_VAR_USED = (uint64)m_cache_num_sets - * (uint64)m_cache_assoc; + uint64_t warmedUpBlocks = 0; + uint64_t totalBlocks M5_VAR_USED = (uint64_t)m_cache_num_sets * + (uint64_t)m_cache_assoc; for (int i = 0; i < m_cache_num_sets; i++) { for (int j = 0; j < m_cache_assoc; j++) { @@ -376,8 +376,7 @@ CacheMemory::recordCacheContents(int cntrl, CacheRecorder* tr) const DPRINTF(RubyCacheTrace, "%s: %lli blocks of %lli total blocks" "recorded %.2f%% \n", name().c_str(), warmedUpBlocks, - (uint64)m_cache_num_sets * (uint64)m_cache_assoc, - (float(warmedUpBlocks)/float(totalBlocks))*100.0); + totalBlocks, (float(warmedUpBlocks) / float(totalBlocks)) * 100.0); } void @@ -410,7 +409,7 @@ CacheMemory::setLocked(Addr address, int context) { DPRINTF(RubyCache, "Setting Lock for addr: %x to %d\n", address, context); assert(address == makeLineAddress(address)); - int64 cacheSet = addressToCacheSet(address); + int64_t cacheSet = addressToCacheSet(address); int loc = findTagInSet(cacheSet, address); assert(loc != -1); m_cache[cacheSet][loc]->setLocked(context); @@ -421,7 +420,7 @@ CacheMemory::clearLocked(Addr address) { DPRINTF(RubyCache, "Clear Lock for addr: %x\n", address); assert(address == makeLineAddress(address)); - int64 cacheSet = addressToCacheSet(address); + int64_t cacheSet = addressToCacheSet(address); int loc = findTagInSet(cacheSet, address); assert(loc != -1); m_cache[cacheSet][loc]->clearLocked(); @@ -431,7 +430,7 @@ bool CacheMemory::isLocked(Addr address, int context) { assert(address == makeLineAddress(address)); - int64 cacheSet = addressToCacheSet(address); + int64_t cacheSet = addressToCacheSet(address); int loc = findTagInSet(cacheSet, address); assert(loc != -1); DPRINTF(RubyCache, "Testing Lock for addr: %llx cur %d con %d\n", @@ -594,13 +593,13 @@ CacheMemory::checkResourceAvailable(CacheResourceType res, Addr addr) } bool -CacheMemory::isBlockInvalid(int64 cache_set, int64 loc) +CacheMemory::isBlockInvalid(int64_t cache_set, int64_t loc) { return (m_cache[cache_set][loc]->m_Permission == AccessPermission_Invalid); } bool -CacheMemory::isBlockNotBusy(int64 cache_set, int64 loc) +CacheMemory::isBlockNotBusy(int64_t cache_set, int64_t loc) { return (m_cache[cache_set][loc]->m_Permission != AccessPermission_Busy); } diff --git a/src/mem/ruby/structures/CacheMemory.hh b/src/mem/ruby/structures/CacheMemory.hh index 6c719cb4f..1af446950 100644 --- a/src/mem/ruby/structures/CacheMemory.hh +++ b/src/mem/ruby/structures/CacheMemory.hh @@ -98,8 +98,8 @@ class CacheMemory : public SimObject Cycles getTagLatency() const { return tagArray.getLatency(); } Cycles getDataLatency() const { return dataArray.getLatency(); } - bool isBlockInvalid(int64 cache_set, int64 loc); - bool isBlockNotBusy(int64 cache_set, int64 loc); + bool isBlockInvalid(int64_t cache_set, int64_t loc); + bool isBlockNotBusy(int64_t cache_set, int64_t loc); // Hook for checkpointing the contents of the cache void recordCacheContents(int cntrl, CacheRecorder* tr) const; @@ -149,12 +149,12 @@ class CacheMemory : public SimObject private: // convert a Address to its location in the cache - int64 addressToCacheSet(Addr address) const; + int64_t addressToCacheSet(Addr address) const; // Given a cache tag: returns the index of the tag in a set. // returns -1 if the tag is not found. - int findTagInSet(int64 line, Addr tag) const; - int findTagInSetIgnorePermissions(int64 cacheSet, Addr tag) const; + int findTagInSet(int64_t line, Addr tag) const; + int findTagInSetIgnorePermissions(int64_t cacheSet, Addr tag) const; // Private copy constructor and assignment operator CacheMemory(const CacheMemory& obj); diff --git a/src/mem/ruby/structures/LRUPolicy.cc b/src/mem/ruby/structures/LRUPolicy.cc index a1e3b277e..1c4990291 100644 --- a/src/mem/ruby/structures/LRUPolicy.cc +++ b/src/mem/ruby/structures/LRUPolicy.cc @@ -50,7 +50,7 @@ LRUReplacementPolicyParams::create() void -LRUPolicy::touch(int64 set, int64 index, Tick time) +LRUPolicy::touch(int64_t set, int64_t index, Tick time) { assert(index >= 0 && index < m_assoc); assert(set >= 0 && set < m_num_sets); @@ -58,13 +58,11 @@ LRUPolicy::touch(int64 set, int64 index, Tick time) m_last_ref_ptr[set][index] = time; } -int64 -LRUPolicy::getVictim(int64 set) const +int64_t +LRUPolicy::getVictim(int64_t set) const { Tick time, smallest_time; - int64 smallest_index; - - smallest_index = 0; + int64_t smallest_index = 0; smallest_time = m_last_ref_ptr[set][0]; for (unsigned i = 0; i < m_assoc; i++) { diff --git a/src/mem/ruby/structures/LRUPolicy.hh b/src/mem/ruby/structures/LRUPolicy.hh index 9a9c9e3eb..388718319 100644 --- a/src/mem/ruby/structures/LRUPolicy.hh +++ b/src/mem/ruby/structures/LRUPolicy.hh @@ -41,8 +41,8 @@ class LRUPolicy : public AbstractReplacementPolicy LRUPolicy(const Params * p); ~LRUPolicy(); - void touch(int64 set, int64 way, Tick time); - int64 getVictim(int64 set) const; + void touch(int64_t set, int64_t way, Tick time); + int64_t getVictim(int64_t set) const; }; #endif // __MEM_RUBY_STRUCTURES_LRUPOLICY_HH__ diff --git a/src/mem/ruby/structures/PseudoLRUPolicy.cc b/src/mem/ruby/structures/PseudoLRUPolicy.cc index 8eee0821b..a2b21a625 100644 --- a/src/mem/ruby/structures/PseudoLRUPolicy.cc +++ b/src/mem/ruby/structures/PseudoLRUPolicy.cc @@ -38,7 +38,7 @@ PseudoLRUPolicy::PseudoLRUPolicy(const Params * p) // associativity cannot exceed capacity of tree representation assert(m_num_sets > 0 && m_assoc > 1 && - m_assoc <= (int64) sizeof(uint64)*4); + m_assoc <= (int64_t) sizeof(uint64_t)*4); m_trees = NULL; m_num_levels = 0; @@ -55,7 +55,7 @@ PseudoLRUPolicy::PseudoLRUPolicy(const Params * p) m_num_levels++; } assert(m_num_levels < sizeof(unsigned int)*4); - m_trees = new uint64[m_num_sets]; + m_trees = new uint64_t[m_num_sets]; for (unsigned i = 0; i < m_num_sets; i++) { m_trees[i] = 0; } @@ -75,7 +75,7 @@ PseudoLRUPolicy::~PseudoLRUPolicy() } void -PseudoLRUPolicy::touch(int64 set, int64 index, Tick time) +PseudoLRUPolicy::touch(int64_t set, int64_t index, Tick time) { assert(index >= 0 && index < m_assoc); assert(set >= 0 && set < m_num_sets); @@ -93,10 +93,10 @@ PseudoLRUPolicy::touch(int64 set, int64 index, Tick time) m_last_ref_ptr[set][index] = time; } -int64 -PseudoLRUPolicy::getVictim(int64 set) const +int64_t +PseudoLRUPolicy::getVictim(int64_t set) const { - int64 index = 0; + int64_t index = 0; int tree_index = 0; int node_val; diff --git a/src/mem/ruby/structures/PseudoLRUPolicy.hh b/src/mem/ruby/structures/PseudoLRUPolicy.hh index fc5add8b1..a96c802b2 100644 --- a/src/mem/ruby/structures/PseudoLRUPolicy.hh +++ b/src/mem/ruby/structures/PseudoLRUPolicy.hh @@ -53,13 +53,13 @@ class PseudoLRUPolicy : public AbstractReplacementPolicy PseudoLRUPolicy(const Params * p); ~PseudoLRUPolicy(); - void touch(int64 set, int64 way, Tick time); - int64 getVictim(int64 set) const; + void touch(int64_t set, int64_t way, Tick time); + int64_t getVictim(int64_t set) const; private: unsigned int m_effective_assoc; /** nearest (to ceiling) power of 2 */ unsigned int m_num_levels; /** number of levels in the tree */ - uint64* m_trees; /** bit representation of the + uint64_t* m_trees; /** bit representation of the * trees, one for each set */ }; diff --git a/src/mem/ruby/structures/RubyMemoryControl.cc b/src/mem/ruby/structures/RubyMemoryControl.cc index 0521aac06..413850627 100644 --- a/src/mem/ruby/structures/RubyMemoryControl.cc +++ b/src/mem/ruby/structures/RubyMemoryControl.cc @@ -176,7 +176,7 @@ void RubyMemoryControl::init() { m_msg_counter = 0; - assert(m_tFaw <= 62); // must fit in a uint64 shift register + assert(m_tFaw <= 62); // must fit in a uint64_t shift register m_total_banks = m_banks_per_rank * m_ranks_per_dimm * m_dimms_per_channel; m_total_ranks = m_ranks_per_dimm * m_dimms_per_channel; @@ -213,7 +213,7 @@ RubyMemoryControl::init() // m_tfaw_count keeps track of how many 1 bits are set // in each shift register. When m_tfaw_count is >= 4, // new activates are not allowed. - m_tfaw_shift = new uint64[m_total_ranks]; + m_tfaw_shift = new uint64_t[m_total_ranks]; m_tfaw_count = new int[m_total_ranks]; for (int i = 0; i < m_total_ranks; i++) { m_tfaw_shift[i] = 0; @@ -236,7 +236,7 @@ RubyMemoryControl::reset() { m_msg_counter = 0; - assert(m_tFaw <= 62); // must fit in a uint64 shift register + assert(m_tFaw <= 62); // must fit in a uint64_t shift register m_total_banks = m_banks_per_rank * m_ranks_per_dimm * m_dimms_per_channel; m_total_ranks = m_ranks_per_dimm * m_dimms_per_channel; diff --git a/src/mem/ruby/structures/RubyMemoryControl.hh b/src/mem/ruby/structures/RubyMemoryControl.hh index c68a2da6c..376ce4d75 100644 --- a/src/mem/ruby/structures/RubyMemoryControl.hh +++ b/src/mem/ruby/structures/RubyMemoryControl.hh @@ -162,11 +162,11 @@ class RubyMemoryControl : public AbstractMemory, public Consumer // Each entry indicates number of address-bus cycles until bank // is reschedulable: - int* m_bankBusyCounter; - int* m_oldRequest; + int *m_bankBusyCounter; + int *m_oldRequest; - uint64* m_tfaw_shift; - int* m_tfaw_count; + uint64_t *m_tfaw_shift; + int *m_tfaw_count; // Each of these indicates number of address-bus cycles until // we can issue a new request of the corresponding type: @@ -182,12 +182,12 @@ class RubyMemoryControl : public AbstractMemory, public Consumer int m_ageCounter; // age of old requests; to detect starvation int m_idleCount; // watchdog timer for shutting down - MemCntrlProfiler* m_profiler_ptr; + MemCntrlProfiler *m_profiler_ptr; class MemCntrlEvent : public Event { public: - MemCntrlEvent(RubyMemoryControl* _mem_cntrl) + MemCntrlEvent(RubyMemoryControl *_mem_cntrl) { mem_cntrl = _mem_cntrl; } -- cgit v1.2.3