From 8e5c441a54b481085d6311f14af66e41b5766f91 Mon Sep 17 00:00:00 2001 From: Brad Beckmann Date: Fri, 20 Aug 2010 11:46:12 -0700 Subject: ruby: fix ruby llsc support to sync sc outcomes Added support so that ruby can determine the outcome of store conditional operations and reflect that outcome to M5 physical memory and cpus. --- src/mem/ruby/system/CacheMemory.cc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'src/mem/ruby/system/CacheMemory.cc') diff --git a/src/mem/ruby/system/CacheMemory.cc b/src/mem/ruby/system/CacheMemory.cc index 9102d1963..604113238 100644 --- a/src/mem/ruby/system/CacheMemory.cc +++ b/src/mem/ruby/system/CacheMemory.cc @@ -353,7 +353,9 @@ CacheMemory::changePermission(const Address& address, lookup(address).m_Permission = new_perm; Index cacheSet = addressToCacheSet(address); int loc = findTagInSet(cacheSet, address); - if (new_perm != AccessPermission_Read_Write) { + if ((new_perm == AccessPermission_Invalid) || + (new_perm == AccessPermission_NotPresent) || + (new_perm == AccessPermission_Stale)) { DPRINTF(RubyCache, "Permission clearing lock for addr: %x\n", address); m_locked[cacheSet][loc] = -1; } -- cgit v1.2.3