From 5ab13e2deb8f904ef2a233749193fa09ea7013c4 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Mon, 22 Mar 2010 18:43:53 -0700 Subject: ruby: style pass --- src/mem/ruby/system/CacheMemory.hh | 209 ++++++++++++++++++------------------- 1 file changed, 101 insertions(+), 108 deletions(-) (limited to 'src/mem/ruby/system/CacheMemory.hh') diff --git a/src/mem/ruby/system/CacheMemory.hh b/src/mem/ruby/system/CacheMemory.hh index 74eb5d68d..bdf2bb25c 100644 --- a/src/mem/ruby/system/CacheMemory.hh +++ b/src/mem/ruby/system/CacheMemory.hh @@ -26,151 +26,144 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* - * CacheMemory.hh - * - * Description: - * - * $Id: CacheMemory.hh,v 3.7 2004/06/18 20:15:15 beckmann Exp $ - * - */ +#ifndef __MEM_RUBY_SYSTEM_CACHEMEMORY_HH__ +#define __MEM_RUBY_SYSTEM_CACHEMEMORY_HH__ -#ifndef CACHEMEMORY_H -#define CACHEMEMORY_H - -#include "sim/sim_object.hh" -#include "params/RubyCache.hh" +#include -#include "mem/ruby/common/Global.hh" +#include "base/hashmap.hh" +#include "mem/gems_common/Vector.hh" #include "mem/protocol/AccessPermission.hh" -#include "mem/ruby/common/Address.hh" -#include "mem/ruby/recorder/CacheRecorder.hh" +#include "mem/protocol/CacheMsg.hh" #include "mem/protocol/CacheRequestType.hh" -#include "mem/gems_common/Vector.hh" -#include "mem/ruby/common/DataBlock.hh" #include "mem/protocol/MachineType.hh" +#include "mem/ruby/common/Address.hh" +#include "mem/ruby/common/DataBlock.hh" +#include "mem/ruby/common/Global.hh" +#include "mem/ruby/profiler/CacheProfiler.hh" +#include "mem/ruby/recorder/CacheRecorder.hh" +#include "mem/ruby/slicc_interface/AbstractCacheEntry.hh" +#include "mem/ruby/slicc_interface/AbstractController.hh" #include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh" -#include "mem/ruby/system/PseudoLRUPolicy.hh" #include "mem/ruby/system/LRUPolicy.hh" -#include "mem/ruby/slicc_interface/AbstractCacheEntry.hh" +#include "mem/ruby/system/PseudoLRUPolicy.hh" #include "mem/ruby/system/System.hh" -#include "mem/ruby/slicc_interface/AbstractController.hh" -#include "mem/ruby/profiler/CacheProfiler.hh" -#include "mem/protocol/CacheMsg.hh" -#include "base/hashmap.hh" -#include - -class CacheMemory : public SimObject { -public: +#include "params/RubyCache.hh" +#include "sim/sim_object.hh" +class CacheMemory : public SimObject +{ + public: typedef RubyCacheParams Params; - // Constructors - CacheMemory(const Params *p); - // CacheMemory(const string & name); - void init(); - - // Destructor - ~CacheMemory(); + CacheMemory(const Params *p); + ~CacheMemory(); - // Public Methods - void printConfig(ostream& out); + void init(); - // perform a cache access and see if we hit or not. Return true on a hit. - bool tryCacheAccess(const Address& address, CacheRequestType type, DataBlock*& data_ptr); + // Public Methods + void printConfig(ostream& out); - // similar to above, but doesn't require full access check - bool testCacheAccess(const Address& address, CacheRequestType type, DataBlock*& data_ptr); + // perform a cache access and see if we hit or not. Return true on a hit. + bool tryCacheAccess(const Address& address, CacheRequestType type, + DataBlock*& data_ptr); - // tests to see if an address is present in the cache - bool isTagPresent(const Address& address) const; + // similar to above, but doesn't require full access check + bool testCacheAccess(const Address& address, CacheRequestType type, + DataBlock*& data_ptr); - // Returns true if there is: - // a) a tag match on this address or there is - // b) an unused line in the same cache "way" - bool cacheAvail(const Address& address) const; + // tests to see if an address is present in the cache + bool isTagPresent(const Address& address) const; - // find an unused entry and sets the tag appropriate for the address - void allocate(const Address& address, AbstractCacheEntry* new_entry); + // Returns true if there is: + // a) a tag match on this address or there is + // b) an unused line in the same cache "way" + bool cacheAvail(const Address& address) const; - // Explicitly free up this address - void deallocate(const Address& address); + // find an unused entry and sets the tag appropriate for the address + void allocate(const Address& address, AbstractCacheEntry* new_entry); - // Returns with the physical address of the conflicting cache line - Address cacheProbe(const Address& address) const; + // Explicitly free up this address + void deallocate(const Address& address); - // looks an address up in the cache - AbstractCacheEntry& lookup(const Address& address); - const AbstractCacheEntry& lookup(const Address& address) const; + // Returns with the physical address of the conflicting cache line + Address cacheProbe(const Address& address) const; - // Get/Set permission of cache block - AccessPermission getPermission(const Address& address) const; - void changePermission(const Address& address, AccessPermission new_perm); + // looks an address up in the cache + AbstractCacheEntry& lookup(const Address& address); + const AbstractCacheEntry& lookup(const Address& address) const; - int getLatency() const { return m_latency; } + // Get/Set permission of cache block + AccessPermission getPermission(const Address& address) const; + void changePermission(const Address& address, AccessPermission new_perm); - // Hook for checkpointing the contents of the cache - void recordCacheContents(CacheRecorder& tr) const; - void setAsInstructionCache(bool is_icache) { m_is_instruction_only_cache = is_icache; } + int getLatency() const { return m_latency; } - // Set this address to most recently used - void setMRU(const Address& address); + // Hook for checkpointing the contents of the cache + void recordCacheContents(CacheRecorder& tr) const; + void + setAsInstructionCache(bool is_icache) + { + m_is_instruction_only_cache = is_icache; + } - void profileMiss(const CacheMsg & msg); + // Set this address to most recently used + void setMRU(const Address& address); - void getMemoryValue(const Address& addr, char* value, - unsigned int size_in_bytes ); - void setMemoryValue(const Address& addr, char* value, - unsigned int size_in_bytes ); + void profileMiss(const CacheMsg & msg); - void setLocked (const Address& addr, int context); - void clearLocked (const Address& addr); - bool isLocked (const Address& addr, int context); - // Print cache contents - void print(ostream& out) const; - void printData(ostream& out) const; + void getMemoryValue(const Address& addr, char* value, + unsigned int size_in_bytes); + void setMemoryValue(const Address& addr, char* value, + unsigned int size_in_bytes); - void clearStats() const; - void printStats(ostream& out) const; + void setLocked (const Address& addr, int context); + void clearLocked (const Address& addr); + bool isLocked (const Address& addr, int context); + // Print cache contents + void print(ostream& out) const; + void printData(ostream& out) const; -private: - // Private Methods + void clearStats() const; + void printStats(ostream& out) const; - // convert a Address to its location in the cache - Index addressToCacheSet(const Address& address) const; + private: + // convert a Address to its location in the cache + Index addressToCacheSet(const Address& address) const; - // Given a cache tag: returns the index of the tag in a set. - // returns -1 if the tag is not found. - int findTagInSet(Index line, const Address& tag) const; - int findTagInSetIgnorePermissions(Index cacheSet, const Address& tag) const; + // Given a cache tag: returns the index of the tag in a set. + // returns -1 if the tag is not found. + int findTagInSet(Index line, const Address& tag) const; + int findTagInSetIgnorePermissions(Index cacheSet, + const Address& tag) const; - // Private copy constructor and assignment operator - CacheMemory(const CacheMemory& obj); - CacheMemory& operator=(const CacheMemory& obj); + // Private copy constructor and assignment operator + CacheMemory(const CacheMemory& obj); + CacheMemory& operator=(const CacheMemory& obj); -private: - const string m_cache_name; - int m_latency; + private: + const string m_cache_name; + int m_latency; - // Data Members (m_prefix) - bool m_is_instruction_only_cache; - bool m_is_data_only_cache; + // Data Members (m_prefix) + bool m_is_instruction_only_cache; + bool m_is_data_only_cache; - // The first index is the # of cache lines. - // The second index is the the amount associativity. - m5::hash_map m_tag_index; - Vector > m_cache; - Vector > m_locked; + // The first index is the # of cache lines. + // The second index is the the amount associativity. + m5::hash_map m_tag_index; + Vector > m_cache; + Vector > m_locked; - AbstractReplacementPolicy *m_replacementPolicy_ptr; + AbstractReplacementPolicy *m_replacementPolicy_ptr; - CacheProfiler* m_profiler_ptr; + CacheProfiler* m_profiler_ptr; - int m_cache_size; - string m_policy; - int m_cache_num_sets; - int m_cache_num_set_bits; - int m_cache_assoc; + int m_cache_size; + string m_policy; + int m_cache_num_sets; + int m_cache_num_set_bits; + int m_cache_assoc; }; -#endif //CACHEMEMORY_H +#endif // __MEM_RUBY_SYSTEM_CACHEMEMORY_HH__ -- cgit v1.2.3