From 2f30950143cc70bc42a3c8a4111d7cf8198ec881 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Mon, 11 May 2009 10:38:43 -0700 Subject: ruby: Import ruby and slicc from GEMS We eventually plan to replace the m5 cache hierarchy with the GEMS hierarchy, but for now we will make both live alongside eachother. --- src/mem/ruby/system/PerfectCacheMemory.hh | 239 ++++++++++++++++++++++++++++++ 1 file changed, 239 insertions(+) create mode 100644 src/mem/ruby/system/PerfectCacheMemory.hh (limited to 'src/mem/ruby/system/PerfectCacheMemory.hh') diff --git a/src/mem/ruby/system/PerfectCacheMemory.hh b/src/mem/ruby/system/PerfectCacheMemory.hh new file mode 100644 index 000000000..590b265c4 --- /dev/null +++ b/src/mem/ruby/system/PerfectCacheMemory.hh @@ -0,0 +1,239 @@ + +/* + * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * PerfectCacheMemory.h + * + * Description: + * + * $Id$ + * + */ + +#ifndef PERFECTCACHEMEMORY_H +#define PERFECTCACHEMEMORY_H + +#include "Global.hh" +#include "Map.hh" +#include "AccessPermission.hh" +#include "RubyConfig.hh" +#include "Address.hh" +#include "interface.hh" +#include "AbstractChip.hh" + +template +class PerfectCacheLineState { +public: + PerfectCacheLineState() { m_permission = AccessPermission_NUM; } + AccessPermission m_permission; + ENTRY m_entry; +}; + +template +class PerfectCacheMemory { +public: + + // Constructors + PerfectCacheMemory(AbstractChip* chip_ptr); + + // Destructor + //~PerfectCacheMemory(); + + // Public Methods + + static void printConfig(ostream& out); + + // perform a cache access and see if we hit or not. Return true on + // a hit. + bool tryCacheAccess(const CacheMsg& msg, bool& block_stc, ENTRY*& entry); + + // tests to see if an address is present in the cache + bool isTagPresent(const Address& address) const; + + // Returns true if there is: + // a) a tag match on this address or there is + // b) an Invalid line in the same cache "way" + bool cacheAvail(const Address& address) const; + + // find an Invalid entry and sets the tag appropriate for the address + void allocate(const Address& address); + + void deallocate(const Address& address); + + // Returns with the physical address of the conflicting cache line + Address cacheProbe(const Address& newAddress) const; + + // looks an address up in the cache + ENTRY& lookup(const Address& address); + const ENTRY& lookup(const Address& address) const; + + // Get/Set permission of cache block + AccessPermission getPermission(const Address& address) const; + void changePermission(const Address& address, AccessPermission new_perm); + + // Print cache contents + void print(ostream& out) const; +private: + // Private Methods + + // Private copy constructor and assignment operator + PerfectCacheMemory(const PerfectCacheMemory& obj); + PerfectCacheMemory& operator=(const PerfectCacheMemory& obj); + + // Data Members (m_prefix) + Map > m_map; + AbstractChip* m_chip_ptr; +}; + +// Output operator declaration +//ostream& operator<<(ostream& out, const PerfectCacheMemory& obj); + +// ******************* Definitions ******************* + +// Output operator definition +template +extern inline +ostream& operator<<(ostream& out, const PerfectCacheMemory& obj) +{ + obj.print(out); + out << flush; + return out; +} + + +// **************************************************************** + +template +extern inline +PerfectCacheMemory::PerfectCacheMemory(AbstractChip* chip_ptr) +{ + m_chip_ptr = chip_ptr; +} + +// STATIC METHODS + +template +extern inline +void PerfectCacheMemory::printConfig(ostream& out) +{ +} + +// PUBLIC METHODS + +template +extern inline +bool PerfectCacheMemory::tryCacheAccess(const CacheMsg& msg, bool& block_stc, ENTRY*& entry) +{ + ERROR_MSG("not implemented"); +} + +// tests to see if an address is present in the cache +template +extern inline +bool PerfectCacheMemory::isTagPresent(const Address& address) const +{ + return m_map.exist(line_address(address)); +} + +template +extern inline +bool PerfectCacheMemory::cacheAvail(const Address& address) const +{ + return true; +} + +// find an Invalid or already allocated entry and sets the tag +// appropriate for the address +template +extern inline +void PerfectCacheMemory::allocate(const Address& address) +{ + PerfectCacheLineState line_state; + line_state.m_permission = AccessPermission_Busy; + line_state.m_entry = ENTRY(); + m_map.add(line_address(address), line_state); +} + +// deallocate entry +template +extern inline +void PerfectCacheMemory::deallocate(const Address& address) +{ + m_map.erase(line_address(address)); +} + +// Returns with the physical address of the conflicting cache line +template +extern inline +Address PerfectCacheMemory::cacheProbe(const Address& newAddress) const +{ + ERROR_MSG("cacheProbe called in perfect cache"); +} + +// looks an address up in the cache +template +extern inline +ENTRY& PerfectCacheMemory::lookup(const Address& address) +{ + return m_map.lookup(line_address(address)).m_entry; +} + +// looks an address up in the cache +template +extern inline +const ENTRY& PerfectCacheMemory::lookup(const Address& address) const +{ + return m_map.lookup(line_address(address)).m_entry; +} + +template +extern inline +AccessPermission PerfectCacheMemory::getPermission(const Address& address) const +{ + return m_map.lookup(line_address(address)).m_permission; +} + +template +extern inline +void PerfectCacheMemory::changePermission(const Address& address, AccessPermission new_perm) +{ + Address line_address = address; + line_address.makeLineAddress(); + PerfectCacheLineState& line_state = m_map.lookup(line_address); + AccessPermission old_perm = line_state.m_permission; + line_state.m_permission = new_perm; +} + +template +extern inline +void PerfectCacheMemory::print(ostream& out) const +{ +} + +#endif //PERFECTCACHEMEMORY_H -- cgit v1.2.3