From cfc268ad9e5b83cac551cae118811e5c86382d9e Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Mon, 30 Jan 2012 05:38:24 -0500 Subject: MEM: Make the RubyPort physMemPort a PioPort instead of M5Port This patch makes the physMemPort of the RubyPort a PioPort rather than an M5Port. This reflects the fact that the M5Port and PioPort have different roles. The M5Port is really a coherent slave that is connected to the CPUs and other coherent masters of the system, e.g. DMA ports. The PioPort, on the other hand, is a master port that is connected to the memory and other slaves, for example the pio devices. This simplifies future changes into master/slave ports and is consistent with the port roles throughout the system. --- src/mem/ruby/system/RubyPort.hh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mem/ruby/system/RubyPort.hh') diff --git a/src/mem/ruby/system/RubyPort.hh b/src/mem/ruby/system/RubyPort.hh index 2ffdef3d9..6df713a13 100644 --- a/src/mem/ruby/system/RubyPort.hh +++ b/src/mem/ruby/system/RubyPort.hh @@ -155,7 +155,7 @@ class RubyPort : public MemObject uint16_t m_port_id; uint64_t m_request_cnt; - M5Port* physMemPort; + PioPort* physMemPort; /*! Vector of CPU Port attached to this Ruby port. */ typedef std::vector::iterator CpuPortIter; -- cgit v1.2.3