From 322b9ca2c5b0465db7086abdc6eadca061932575 Mon Sep 17 00:00:00 2001 From: Lisa Hsu Date: Thu, 31 Mar 2011 17:17:57 -0700 Subject: Ruby: Add new object called WireBuffer to mimic a Wire. This is a substitute for MessageBuffers between controllers where you don't want messages to actually go through the Network, because requests/responses can always get reordered wrt to one another (even if you turn off Randomization and turn on Ordered) because you are, after all, going through a network with contention. For systems where you model multiple controllers that are very tightly coupled and do not actually go through a network, it is a pain to have to write a coherence protocol to account for mixed up request/response orderings despite the fact that it's completely unrealistic. This is *not* meant as a substitute for real MessageBuffers when messages do in fact go over a network. --- src/mem/ruby/system/SConscript | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/mem/ruby/system/SConscript') diff --git a/src/mem/ruby/system/SConscript b/src/mem/ruby/system/SConscript index edc9d451f..f1e7c425c 100644 --- a/src/mem/ruby/system/SConscript +++ b/src/mem/ruby/system/SConscript @@ -37,6 +37,7 @@ SimObject('Cache.py') SimObject('Sequencer.py') SimObject('DirectoryMemory.py') SimObject('MemoryControl.py') +SimObject('WireBuffer.py') SimObject('RubySystem.py') Source('DMASequencer.cc') @@ -44,6 +45,7 @@ Source('DirectoryMemory.cc') Source('SparseMemory.cc') Source('CacheMemory.cc') Source('MemoryControl.cc') +Source('WireBuffer.cc') Source('MemoryNode.cc') Source('PersistentTable.cc') Source('RubyPort.cc') -- cgit v1.2.3