From 98c94cfe3ce83634f3bad79ca18263f42e36ca6a Mon Sep 17 00:00:00 2001
From: Steve Reinhardt <steve.reinhardt@amd.com>
Date: Fri, 29 Jan 2010 20:29:17 -0800
Subject: ruby: Convert most Ruby objects to M5 SimObjects. The necessary
 companion conversion of Ruby objects generated by SLICC are converted to M5
 SimObjects in the following patch, so this patch alone does not compile.
 Conversion of Garnet network models is also handled in a separate patch; that
 code is temporarily disabled from compiling to allow testing of interim code.

---
 src/mem/ruby/system/Sequencer.hh | 12 +++++-------
 1 file changed, 5 insertions(+), 7 deletions(-)

(limited to 'src/mem/ruby/system/Sequencer.hh')

diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh
index 1621bbbdc..d2dc5bbb3 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -51,7 +51,8 @@ class DataBlock;
 class CacheMsg;
 class MachineID;
 class CacheMemory;
-class AbstractController;
+
+class RubySequencerParams;
 
 struct SequencerRequest {
   RubyRequest ruby_request;
@@ -65,11 +66,11 @@ struct SequencerRequest {
 
 std::ostream& operator<<(std::ostream& out, const SequencerRequest& obj);
 
-class Sequencer : public Consumer, public RubyPort {
+class Sequencer : public RubyPort, public Consumer {
 public:
+    typedef RubySequencerParams Params;
   // Constructors
-  Sequencer(const string & name);
-  void init(const vector<string> & argv);
+  Sequencer(const Params *);
 
   // Destructor
   ~Sequencer();
@@ -114,13 +115,10 @@ private:
   int m_max_outstanding_requests;
   int m_deadlock_threshold;
 
-  AbstractController* m_controller;
-  MessageBuffer* m_mandatory_q_ptr;
   CacheMemory* m_dataCache_ptr;
   CacheMemory* m_instCache_ptr;
 
   // indicates what processor on the chip this sequencer is associated with
-  int m_version;
   int m_controller_type;
 
   Map<Address, SequencerRequest*> m_writeRequestTable;
-- 
cgit v1.2.3