From d3d24835bcc03ecf312ac6ba7df114656770730f Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Thu, 7 Mar 2019 03:02:35 -0800 Subject: arch, cpu, dev, gpu, mem, sim, python: start using getPort. Replace the getMasterPort, getSlavePort, and getEthPort functions with getPort, and remove extraneous mechanisms that are no longer necessary. Change-Id: Iab7e3c02d2f3a0cf33e7e824e18c28646b5bc318 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17040 Reviewed-by: Daniel Carvalho Reviewed-by: Andreas Sandberg Maintainer: Andreas Sandberg --- src/mem/ruby/system/RubyPort.cc | 52 ++++++++++++++--------------------------- src/mem/ruby/system/RubyPort.hh | 6 ++--- 2 files changed, 20 insertions(+), 38 deletions(-) (limited to 'src/mem/ruby/system') diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc index 84a70c0f1..795b473c7 100644 --- a/src/mem/ruby/system/RubyPort.cc +++ b/src/mem/ruby/system/RubyPort.cc @@ -87,53 +87,37 @@ RubyPort::init() m_mandatory_q_ptr = m_controller->getMandatoryQueue(); } -BaseMasterPort & -RubyPort::getMasterPort(const std::string &if_name, PortID idx) +Port & +RubyPort::getPort(const std::string &if_name, PortID idx) { if (if_name == "mem_master_port") { return memMasterPort; - } - - if (if_name == "pio_master_port") { + } else if (if_name == "pio_master_port") { return pioMasterPort; - } - - // used by the x86 CPUs to connect the interrupt PIO and interrupt slave - // port - if (if_name != "master") { - // pass it along to our super class - return MemObject::getMasterPort(if_name, idx); - } else { + } else if (if_name == "mem_slave_port") { + return memSlavePort; + } else if (if_name == "pio_slave_port") { + return pioSlavePort; + } else if (if_name == "master") { + // used by the x86 CPUs to connect the interrupt PIO and interrupt + // slave port if (idx >= static_cast(master_ports.size())) { - panic("RubyPort::getMasterPort: unknown index %d\n", idx); + panic("RubyPort::getPort master: unknown index %d\n", idx); } return *master_ports[idx]; - } -} - -BaseSlavePort & -RubyPort::getSlavePort(const std::string &if_name, PortID idx) -{ - if (if_name == "mem_slave_port") { - return memSlavePort; - } - - if (if_name == "pio_slave_port") - return pioSlavePort; - - // used by the CPUs to connect the caches to the interconnect, and - // for the x86 case also the interrupt master - if (if_name != "slave") { - // pass it along to our super class - return MemObject::getSlavePort(if_name, idx); - } else { + } else if (if_name == "slave") { + // used by the CPUs to connect the caches to the interconnect, and + // for the x86 case also the interrupt master if (idx >= static_cast(slave_ports.size())) { - panic("RubyPort::getSlavePort: unknown index %d\n", idx); + panic("RubyPort::getPort slave: unknown index %d\n", idx); } return *slave_ports[idx]; } + + // pass it along to our super class + return MemObject::getPort(if_name, idx); } RubyPort::PioMasterPort::PioMasterPort(const std::string &_name, diff --git a/src/mem/ruby/system/RubyPort.hh b/src/mem/ruby/system/RubyPort.hh index 146443282..922b3a973 100644 --- a/src/mem/ruby/system/RubyPort.hh +++ b/src/mem/ruby/system/RubyPort.hh @@ -148,10 +148,8 @@ class RubyPort : public MemObject void init() override; - BaseMasterPort &getMasterPort(const std::string &if_name, - PortID idx = InvalidPortID) override; - BaseSlavePort &getSlavePort(const std::string &if_name, - PortID idx = InvalidPortID) override; + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; virtual RequestStatus makeRequest(PacketPtr pkt) = 0; virtual int outstandingCount() const = 0; -- cgit v1.2.3