From 93f2f69657d0a2420a2c86b71505e6d27e6e2a38 Mon Sep 17 00:00:00 2001 From: Daniel Sanchez Date: Mon, 11 May 2009 10:38:46 -0700 Subject: ruby: Working M5 interface and updated Ruby interface. This changeset also includes a lot of work from Derek Hower RubyMemory is now both a driver for Ruby and a port for M5. Changed makeRequest/hitCallback interface. Brought packets (superficially) into the sequencer. Modified tester infrastructure to be packet based. and Ruby can be used together through the example ruby_se.py script. SPARC parallel applications work, and the timing *seems* right from combined M5/Ruby debug traces. To run, % build/ALPHA_SE/m5.debug configs/example/ruby_se.py -c tests/test-progs/hello/bin/alpha/linux/hello -n 4 -t --- src/mem/ruby/tester/Check.cc | 77 +++++++++++++++++++++--- src/mem/ruby/tester/DetermGETXGenerator.cc | 11 +++- src/mem/ruby/tester/DetermInvGenerator.cc | 21 ++++++- src/mem/ruby/tester/DetermSeriesGETSGenerator.cc | 11 +++- src/mem/ruby/tester/DeterministicDriver.cc | 15 +++-- src/mem/ruby/tester/DeterministicDriver.hh | 3 +- src/mem/ruby/tester/RequestGenerator.cc | 30 ++++++++- src/mem/ruby/tester/SyntheticDriver.cc | 19 +++--- src/mem/ruby/tester/SyntheticDriver.hh | 2 +- src/mem/ruby/tester/main.cc | 5 +- 10 files changed, 159 insertions(+), 35 deletions(-) (limited to 'src/mem/ruby/tester') diff --git a/src/mem/ruby/tester/Check.cc b/src/mem/ruby/tester/Check.cc index ea26489a3..b9e7e3c10 100644 --- a/src/mem/ruby/tester/Check.cc +++ b/src/mem/ruby/tester/Check.cc @@ -37,6 +37,7 @@ #include "mem/ruby/system/System.hh" #include "mem/ruby/common/SubBlock.hh" #include "mem/protocol/Chip.hh" +#include "mem/packet.hh" Check::Check(const Address& address, const Address& pc) { @@ -84,10 +85,29 @@ void Check::initiatePrefetch(Sequencer* targetSequencer_ptr) } else { type = CacheRequestType_ST; } + + Addr data_addr = m_address.getAddress(); + Addr pc_addr = m_pc.getAddress(); + Request request(0, data_addr, 0, Flags(Request::PREFETCH), pc_addr, 0, 0); + MemCmd::Command command; + if (type == CacheRequestType_IFETCH) { + command = MemCmd::ReadReq; + request.setFlags(Request::INST_FETCH); + } else if (type == CacheRequestType_LD || type == CacheRequestType_IFETCH) { + command = MemCmd::ReadReq; + } else if (type == CacheRequestType_ST) { + command = MemCmd::WriteReq; + } else if (type == CacheRequestType_ATOMIC) { + command = MemCmd::SwapReq; // TODO -- differentiate between atomic types + } else { + assert(false); + } + + Packet pkt(&request, command, 0); // TODO -- make dest a real NodeID + assert(targetSequencer_ptr != NULL); - CacheMsg request(m_address, m_address, type, m_pc, m_access_mode, 0, PrefetchBit_Yes, 0, Address(0), 0 /* only 1 SMT thread */); - if (targetSequencer_ptr->isReady(request)) { - targetSequencer_ptr->makeRequest(request); + if (targetSequencer_ptr->isReady(&pkt)) { + targetSequencer_ptr->makeRequest(&pkt); } } @@ -109,15 +129,34 @@ void Check::initiateAction() type = CacheRequestType_ATOMIC; } - CacheMsg request(Address(m_address.getAddress()+m_store_count), Address(m_address.getAddress()+m_store_count), type, m_pc, m_access_mode, 1, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */); + Addr data_addr = m_address.getAddress()+m_store_count; + Addr pc_addr = m_pc.getAddress(); + Request request(0, data_addr, 1, Flags(), pc_addr, 0, 0); + MemCmd::Command command; + if (type == CacheRequestType_IFETCH) { + command = MemCmd::ReadReq; + request.setFlags(Request::INST_FETCH); + } else if (type == CacheRequestType_LD || type == CacheRequestType_IFETCH) { + command = MemCmd::ReadReq; + } else if (type == CacheRequestType_ST) { + command = MemCmd::WriteReq; + } else if (type == CacheRequestType_ATOMIC) { + command = MemCmd::SwapReq; // TODO -- differentiate between atomic types + } else { + assert(false); + } + + Packet pkt(&request, command, 0); // TODO -- make dest a real NodeID + Sequencer* sequencer_ptr = initiatingSequencer(); - if (sequencer_ptr->isReady(request) == false) { + if (sequencer_ptr->isReady(&pkt) == false) { DEBUG_MSG(TESTER_COMP, MedPrio, "failed to initiate action - sequencer not ready\n"); } else { DEBUG_MSG(TESTER_COMP, MedPrio, "initiating action - successful\n"); DEBUG_EXPR(TESTER_COMP, MedPrio, m_status); m_status = TesterStatus_Action_Pending; - sequencer_ptr->makeRequest(request); + + sequencer_ptr->makeRequest(&pkt); } DEBUG_EXPR(TESTER_COMP, MedPrio, m_status); } @@ -132,15 +171,35 @@ void Check::initiateCheck() type = CacheRequestType_IFETCH; } - CacheMsg request(m_address, m_address, type, m_pc, m_access_mode, CHECK_SIZE, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */); + + Addr data_addr = m_address.getAddress()+m_store_count; + Addr pc_addr = m_pc.getAddress(); + Request request(0, data_addr, CHECK_SIZE, Flags(), pc_addr, 0, 0); + MemCmd::Command command; + if (type == CacheRequestType_IFETCH) { + command = MemCmd::ReadReq; + request.setFlags(Request::INST_FETCH); + } else if (type == CacheRequestType_LD || type == CacheRequestType_IFETCH) { + command = MemCmd::ReadReq; + } else if (type == CacheRequestType_ST) { + command = MemCmd::WriteReq; + } else if (type == CacheRequestType_ATOMIC) { + command = MemCmd::SwapReq; // TODO -- differentiate between atomic types + } else { + assert(false); + } + + Packet pkt(&request, command, 0); // TODO -- make dest a real NodeID + Sequencer* sequencer_ptr = initiatingSequencer(); - if (sequencer_ptr->isReady(request) == false) { + if (sequencer_ptr->isReady(&pkt) == false) { DEBUG_MSG(TESTER_COMP, MedPrio, "failed to initiate check - sequencer not ready\n"); } else { DEBUG_MSG(TESTER_COMP, MedPrio, "initiating check - successful\n"); DEBUG_MSG(TESTER_COMP, MedPrio, m_status); m_status = TesterStatus_Check_Pending; - sequencer_ptr->makeRequest(request); + + sequencer_ptr->makeRequest(&pkt); } DEBUG_MSG(TESTER_COMP, MedPrio, m_status); } diff --git a/src/mem/ruby/tester/DetermGETXGenerator.cc b/src/mem/ruby/tester/DetermGETXGenerator.cc index d496cbe3a..e4d8addd2 100644 --- a/src/mem/ruby/tester/DetermGETXGenerator.cc +++ b/src/mem/ruby/tester/DetermGETXGenerator.cc @@ -44,6 +44,7 @@ #include "mem/ruby/common/SubBlock.hh" #include "mem/ruby/tester/DeterministicDriver.hh" #include "mem/protocol/Chip.hh" +#include "mem/packet.hh" DetermGETXGenerator::DetermGETXGenerator(NodeID node, DeterministicDriver& driver) : m_driver(driver) @@ -137,7 +138,15 @@ void DetermGETXGenerator::pickAddress() void DetermGETXGenerator::initiateStore() { DEBUG_MSG(TESTER_COMP, MedPrio, "initiating Store"); - sequencer()->makeRequest(CacheMsg(m_address, m_address, CacheRequestType_ST, Address(3), AccessModeType_UserMode, 1, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */)); + + Addr data_addr = m_address.getAddress(); + Request request(0, data_addr, 1, Flags(), 3, 0, 0); + MemCmd::Command command; + command = MemCmd::WriteReq; + + Packet pkt(&request, command, 0); // TODO -- make dest a real NodeID + + sequencer()->makeRequest(&pkt); } Sequencer* DetermGETXGenerator::sequencer() const diff --git a/src/mem/ruby/tester/DetermInvGenerator.cc b/src/mem/ruby/tester/DetermInvGenerator.cc index 89d70d91a..bafaa18ae 100644 --- a/src/mem/ruby/tester/DetermInvGenerator.cc +++ b/src/mem/ruby/tester/DetermInvGenerator.cc @@ -179,13 +179,30 @@ void DetermInvGenerator::pickLoadAddress() void DetermInvGenerator::initiateLoad() { DEBUG_MSG(TESTER_COMP, MedPrio, "initiating Load"); - sequencer()->makeRequest(CacheMsg(m_address, m_address, CacheRequestType_LD, Address(1), AccessModeType_UserMode, 1, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */)); + + Addr data_addr = m_address.getAddress(); + Request request(0, data_addr, 1, Flags(), 1, 0, 0); + MemCmd::Command command; + command = MemCmd::ReadReq; + + Packet pkt(&request, command, 0); // TODO -- make dest a real NodeID + + sequencer()->makeRequest(&pkt); + } void DetermInvGenerator::initiateStore() { DEBUG_MSG(TESTER_COMP, MedPrio, "initiating Store"); - sequencer()->makeRequest(CacheMsg(m_address, m_address, CacheRequestType_ST, Address(3), AccessModeType_UserMode, 1, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */)); + + Addr data_addr = m_address.getAddress(); + Request request(0, data_addr, 1, Flags(), 3, 0, 0); + MemCmd::Command command; + command = MemCmd::WriteReq; + + Packet pkt(&request, command, 0); // TODO -- make dest a real NodeID + + sequencer()->makeRequest(&pkt); } Sequencer* DetermInvGenerator::sequencer() const diff --git a/src/mem/ruby/tester/DetermSeriesGETSGenerator.cc b/src/mem/ruby/tester/DetermSeriesGETSGenerator.cc index 67fca6fe0..5adc7aa5c 100644 --- a/src/mem/ruby/tester/DetermSeriesGETSGenerator.cc +++ b/src/mem/ruby/tester/DetermSeriesGETSGenerator.cc @@ -135,7 +135,16 @@ void DetermSeriesGETSGenerator::pickAddress() void DetermSeriesGETSGenerator::initiateLoad() { DEBUG_MSG(TESTER_COMP, MedPrio, "initiating Load"); - sequencer()->makeRequest(CacheMsg(m_address, m_address, CacheRequestType_IFETCH, Address(3), AccessModeType_UserMode, 1, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */)); + + Addr data_addr = m_address.getAddress(); + Request request(0, data_addr, 1, Flags(), 3, 0, 0); + MemCmd::Command command; + command = MemCmd::ReadReq; + request.setFlags(Request::INST_FETCH); + + Packet pkt(&request, command, 0); // TODO -- make dest a real NodeID + + sequencer()->makeRequest(&pkt); } Sequencer* DetermSeriesGETSGenerator::sequencer() const diff --git a/src/mem/ruby/tester/DeterministicDriver.cc b/src/mem/ruby/tester/DeterministicDriver.cc index 7b7d0c9d2..762672118 100644 --- a/src/mem/ruby/tester/DeterministicDriver.cc +++ b/src/mem/ruby/tester/DeterministicDriver.cc @@ -42,6 +42,7 @@ #include "mem/ruby/tester/DetermSeriesGETSGenerator.hh" #include "mem/ruby/common/SubBlock.hh" #include "mem/protocol/Chip.hh" +#include "mem/packet.hh" DeterministicDriver::DeterministicDriver(RubySystem* sys_ptr) { @@ -99,13 +100,17 @@ DeterministicDriver::~DeterministicDriver() } } -void DeterministicDriver::hitCallback(NodeID proc, SubBlock& data, CacheRequestType type, int thread) +void +DeterministicDriver::hitCallback(Packet * pkt) { - DEBUG_EXPR(TESTER_COMP, MedPrio, data); - + NodeID proc = pkt->req->contextId(); + SubBlock data(Address(pkt->getAddr()), pkt->req->getSize()); + if (pkt->hasData()) { + for (int i = 0; i < pkt->req->getSize(); i++) { + data.setByte(i, *(pkt->getPtr()+i)); + } + } m_generator_vector[proc]->performCallback(proc, data); - - // Mark that we made progress m_last_progress_vector[proc] = g_eventQueue_ptr->getTime(); } diff --git a/src/mem/ruby/tester/DeterministicDriver.hh b/src/mem/ruby/tester/DeterministicDriver.hh index d253b7e51..710da7922 100644 --- a/src/mem/ruby/tester/DeterministicDriver.hh +++ b/src/mem/ruby/tester/DeterministicDriver.hh @@ -44,6 +44,7 @@ class RubySystem; class SpecifiedGenerator; +class Packet; class DeterministicDriver : public Driver, public Consumer { public: @@ -69,7 +70,7 @@ public: void recordLoadLatency(Time time); void recordStoreLatency(Time time); - void hitCallback(NodeID proc, SubBlock& data, CacheRequestType type, int thread); + void hitCallback(Packet* pkt); void wakeup(); void printStats(ostream& out) const; void clearStats() {} diff --git a/src/mem/ruby/tester/RequestGenerator.cc b/src/mem/ruby/tester/RequestGenerator.cc index c1772f905..4ee24544f 100644 --- a/src/mem/ruby/tester/RequestGenerator.cc +++ b/src/mem/ruby/tester/RequestGenerator.cc @@ -169,19 +169,43 @@ void RequestGenerator::pickAddress() void RequestGenerator::initiateTest() { DEBUG_MSG(TESTER_COMP, MedPrio, "initiating Test"); - sequencer()->makeRequest(CacheMsg(m_address, m_address, CacheRequestType_LD, Address(1), AccessModeType_UserMode, 1, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */)); + + Addr data_addr = m_address.getAddress(); + Request request(0, data_addr, 1, Flags(), 1, 0, 0); + MemCmd::Command command; + command = MemCmd::ReadReq; + + Packet pkt(&request, command, 0); // TODO -- make dest a real NodeID + + sequencer()->makeRequest(&pkt); } void RequestGenerator::initiateSwap() { DEBUG_MSG(TESTER_COMP, MedPrio, "initiating Swap"); - sequencer()->makeRequest(CacheMsg(m_address, m_address, CacheRequestType_ATOMIC, Address(2), AccessModeType_UserMode, 1, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */)); + + Addr data_addr = m_address.getAddress(); + Request request(0, data_addr, 1, Flags(), 2, 0, 0); + MemCmd::Command command; + command = MemCmd::SwapReq; + + Packet pkt(&request, command, 0); // TODO -- make dest a real NodeID + + sequencer()->makeRequest(&pkt); } void RequestGenerator::initiateRelease() { DEBUG_MSG(TESTER_COMP, MedPrio, "initiating Release"); - sequencer()->makeRequest(CacheMsg(m_address, m_address, CacheRequestType_ST, Address(3), AccessModeType_UserMode, 1, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */)); + + Addr data_addr = m_address.getAddress(); + Request request(0, data_addr, 1, Flags(), 3, 0, 0); + MemCmd::Command command; + command = MemCmd::WriteReq; + + Packet pkt(&request, command, 0); // TODO -- make dest a real NodeID + + sequencer()->makeRequest(&pkt); } Sequencer* RequestGenerator::sequencer() const diff --git a/src/mem/ruby/tester/SyntheticDriver.cc b/src/mem/ruby/tester/SyntheticDriver.cc index 081fc9d5e..f19baa202 100644 --- a/src/mem/ruby/tester/SyntheticDriver.cc +++ b/src/mem/ruby/tester/SyntheticDriver.cc @@ -75,18 +75,17 @@ SyntheticDriver::~SyntheticDriver() } } -void SyntheticDriver::hitCallback(NodeID proc, SubBlock& data, CacheRequestType type, int thread) +void +SyntheticDriver::hitCallback(Packet * pkt) { - DEBUG_EXPR(TESTER_COMP, MedPrio, data); - //cout << " " << proc << " in S.D. hitCallback" << endl; - if(XACT_MEMORY){ - //XactRequestGenerator* reqGen = static_cast(m_request_generator_vector[proc]); - //reqGen->performCallback(proc, data); - } else { - m_request_generator_vector[proc]->performCallback(proc, data); + NodeID proc = pkt->req->contextId(); + SubBlock data(Address(pkt->getAddr()), pkt->req->getSize()); + if (pkt->hasData()) { + for (int i = 0; i < pkt->req->getSize(); i++) { + data.setByte(i, *(pkt->getPtr()+i)); + } } - - // Mark that we made progress + m_request_generator_vector[proc]->performCallback(proc, data); m_last_progress_vector[proc] = g_eventQueue_ptr->getTime(); } diff --git a/src/mem/ruby/tester/SyntheticDriver.hh b/src/mem/ruby/tester/SyntheticDriver.hh index dc0f1be1d..18c463e88 100644 --- a/src/mem/ruby/tester/SyntheticDriver.hh +++ b/src/mem/ruby/tester/SyntheticDriver.hh @@ -60,7 +60,7 @@ public: void recordSwapLatency(Time time); void recordReleaseLatency(Time time); - void hitCallback(NodeID proc, SubBlock& data, CacheRequestType type, int thread); + void hitCallback(Packet* pkt); void conflictCallback(NodeID proc, SubBlock& data, CacheRequestType type, int thread) {assert(0);} void abortCallback(NodeID proc, SubBlock& data, CacheRequestType type, int thread); void wakeup(); diff --git a/src/mem/ruby/tester/main.cc b/src/mem/ruby/tester/main.cc index 5e77488e9..ba835b488 100644 --- a/src/mem/ruby/tester/main.cc +++ b/src/mem/ruby/tester/main.cc @@ -35,7 +35,7 @@ #include "mem/ruby/tester/main.hh" #include "mem/ruby/eventqueue/RubyEventQueue.hh" #include "mem/ruby/config/RubyConfig.hh" -#include "mem/ruby/tester/test_framework.hh" +//#include "mem/ruby/tester/test_framework.hh" // ******************* // *** tester main *** @@ -43,5 +43,6 @@ int main(int argc, char *argv[]) { - tester_main(argc, argv); + //dsm: PRUNED + //tester_main(argc, argv); } -- cgit v1.2.3