From 5060e572ca07b98f7d84679bac81c0151dee46b9 Mon Sep 17 00:00:00 2001 From: Nilay Vaish Date: Fri, 14 Aug 2015 19:28:43 -0500 Subject: ruby: call setMRU from L1 controllers, not from sequencer Currently the sequencer calls the function setMRU that updates the replacement policy structures with the first level caches. While functionally this is correct, the problem is that this requires calling findTagInSet() which is an expensive function. This patch removes the calls to setMRU from the sequencer. All controllers should now update the replacement policy on their own. The set and the way index for a given cache entry can be found within the AbstractCacheEntry structure. Use these indicies to update the replacement policy structures. --- src/mem/ruby/structures/CacheMemory.cc | 8 ++++++++ src/mem/ruby/structures/CacheMemory.hh | 2 ++ src/mem/ruby/system/Sequencer.cc | 12 ++++-------- 3 files changed, 14 insertions(+), 8 deletions(-) (limited to 'src/mem/ruby') diff --git a/src/mem/ruby/structures/CacheMemory.cc b/src/mem/ruby/structures/CacheMemory.cc index ab2647759..931f58a8e 100644 --- a/src/mem/ruby/structures/CacheMemory.cc +++ b/src/mem/ruby/structures/CacheMemory.cc @@ -343,6 +343,14 @@ CacheMemory::setMRU(Addr address) m_replacementPolicy_ptr->touch(cacheSet, loc, curTick()); } +void +CacheMemory::setMRU(const AbstractCacheEntry *e) +{ + uint32_t cacheSet = e->getSetIndex(); + uint32_t loc = e->getWayIndex(); + m_replacementPolicy_ptr->touch(cacheSet, loc, curTick()); +} + void CacheMemory::recordCacheContents(int cntrl, CacheRecorder* tr) const { diff --git a/src/mem/ruby/structures/CacheMemory.hh b/src/mem/ruby/structures/CacheMemory.hh index 1af446950..7ce674e61 100644 --- a/src/mem/ruby/structures/CacheMemory.hh +++ b/src/mem/ruby/structures/CacheMemory.hh @@ -106,6 +106,8 @@ class CacheMemory : public SimObject // Set this address to most recently used void setMRU(Addr address); + // Set this entry to most recently used + void setMRU(const AbstractCacheEntry *e); // Functions for locking and unlocking cache lines corresponding to the // provided address. These are required for supporting atomic memory diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc index b21c70743..740db7d8d 100644 --- a/src/mem/ruby/system/Sequencer.cc +++ b/src/mem/ruby/system/Sequencer.cc @@ -496,19 +496,15 @@ Sequencer::hitCallback(SequencerRequest* srequest, DataBlock& data, const Cycles forwardRequestTime, const Cycles firstResponseTime) { + warn_once("Replacement policy updates recently became the responsibility " + "of SLICC state machines. Make sure to setMRU() near callbacks " + "in .sm files!"); + PacketPtr pkt = srequest->pkt; Addr request_address(pkt->getAddr()); - Addr request_line_address = makeLineAddress(pkt->getAddr()); RubyRequestType type = srequest->m_type; Cycles issued_time = srequest->issue_time; - // Set this cache entry to the most recently used - if (type == RubyRequestType_IFETCH) { - m_instCache_ptr->setMRU(request_line_address); - } else { - m_dataCache_ptr->setMRU(request_line_address); - } - assert(curCycle() >= issued_time); Cycles total_latency = curCycle() - issued_time; -- cgit v1.2.3