From 63563c9df2eca46231768a448e981e8bb7856655 Mon Sep 17 00:00:00 2001 From: Nilay Vaish Date: Mon, 23 Jan 2012 11:07:14 -0600 Subject: O3, Ruby: Forward invalidations from Ruby to O3 CPU This patch implements the functionality for forwarding invalidations and replacements from the L1 cache of the Ruby memory system to the O3 CPU. The implementation adds a list of ports to RubyPort. Whenever a replacement or an invalidation is performed, the L1 cache forwards this to all the ports, which is the LSQ in case of the O3 CPU. --- src/mem/ruby/system/RubyPort.cc | 12 ++++++++++++ src/mem/ruby/system/RubyPort.hh | 4 +++- src/mem/ruby/system/Sequencer.cc | 6 ++++++ src/mem/ruby/system/Sequencer.hh | 2 +- 4 files changed, 22 insertions(+), 2 deletions(-) (limited to 'src/mem/ruby') diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc index ce9973402..b60ca2a07 100644 --- a/src/mem/ruby/system/RubyPort.cc +++ b/src/mem/ruby/system/RubyPort.cc @@ -1,5 +1,6 @@ /* * Copyright (c) 2009 Advanced Micro Devices, Inc. + * Copyright (c) 2011 Mark D. Hill and David A. Wood * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -682,3 +683,14 @@ RubyPort::M5Port::deviceBlockSize() const { return (unsigned) RubySystem::getBlockSizeBytes(); } + +void +RubyPort::ruby_eviction_callback(const Address& address) +{ + DPRINTF(RubyPort, "Sending invalidations.\n"); + Request req(address.getAddress(), 0, 0); + for (CpuPortIter it = cpu_ports.begin(); it != cpu_ports.end(); it++) { + Packet *pkt = new Packet(&req, MemCmd::InvalidationReq, -1); + (*it)->sendTiming(pkt); + } +} diff --git a/src/mem/ruby/system/RubyPort.hh b/src/mem/ruby/system/RubyPort.hh index d8dbe0cda..2ffdef3d9 100644 --- a/src/mem/ruby/system/RubyPort.hh +++ b/src/mem/ruby/system/RubyPort.hh @@ -1,5 +1,6 @@ /* * Copyright (c) 2009 Advanced Micro Devices, Inc. + * Copyright (c) 2011 Mark D. Hill and David A. Wood * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -58,6 +59,7 @@ class RubyPort : public MemObject RubySystem*_system, bool _access_phys_mem); bool sendTiming(PacketPtr pkt); void hitCallback(PacketPtr pkt); + void evictionCallback(const Address& address); unsigned deviceBlockSize() const; bool onRetryList() @@ -129,8 +131,8 @@ class RubyPort : public MemObject protected: const std::string m_name; void ruby_hit_callback(PacketPtr pkt); - void hit(PacketPtr pkt); void testDrainComplete(); + void ruby_eviction_callback(const Address& address); int m_version; AbstractController* m_controller; diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc index 3f9ceb34d..1cd54d45c 100644 --- a/src/mem/ruby/system/Sequencer.cc +++ b/src/mem/ruby/system/Sequencer.cc @@ -733,3 +733,9 @@ Sequencer::checkCoherence(const Address& addr) g_system_ptr->checkGlobalCoherenceInvariant(addr); #endif } + +void +Sequencer::evictionCallback(const Address& address) +{ + ruby_eviction_callback(address); +} diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh index 4a6d46c01..e262e32e8 100644 --- a/src/mem/ruby/system/Sequencer.hh +++ b/src/mem/ruby/system/Sequencer.hh @@ -117,6 +117,7 @@ class Sequencer : public RubyPort, public Consumer void markRemoved(); void removeRequest(SequencerRequest* request); + void evictionCallback(const Address& address); private: void issueRequest(PacketPtr pkt, RubyRequestType type); @@ -181,4 +182,3 @@ operator<<(std::ostream& out, const Sequencer& obj) } #endif // __MEM_RUBY_SYSTEM_SEQUENCER_HH__ - -- cgit v1.2.3