From 03a1aed803ed0d8510a5cf76994b203d3ca3af02 Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Sun, 23 Mar 2014 11:12:06 -0400 Subject: mem: DRAM controller tidying up Minor tidying up and removing of redundant code, including the printing of queue state every million accesses. --- src/mem/simple_dram.hh | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'src/mem/simple_dram.hh') diff --git a/src/mem/simple_dram.hh b/src/mem/simple_dram.hh index 7f58843aa..e3755fec0 100644 --- a/src/mem/simple_dram.hh +++ b/src/mem/simple_dram.hh @@ -353,7 +353,8 @@ class SimpleDRAM : public AbstractMemory * @param isRead Is the request for a read or a write to DRAM * @return A DRAMPacket pointer with the decoded information */ - DRAMPacket* decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned int size, bool isRead); + DRAMPacket* decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned int size, + bool isRead); /** * The memory schduler/arbiter - picks which read request needs to @@ -430,6 +431,10 @@ class SimpleDRAM : public AbstractMemory void recordActivate(Tick act_tick, uint8_t rank, uint8_t bank); void printParams() const; + + /** + * Used for debugging to observe the contents of the queues. + */ void printQs() const; /** @@ -533,9 +538,7 @@ class SimpleDRAM : public AbstractMemory */ Tick busBusyUntil; - Tick writeStartTime; Tick prevArrival; - int numReqs; // The absolute soonest you have to start thinking about the // next request is the longest access time that can occur before -- cgit v1.2.3