From eaa37e611f07a41d97a078bf2588bfe745d83751 Mon Sep 17 00:00:00 2001 From: Ani Udipi Date: Thu, 31 Jan 2013 07:49:14 -0500 Subject: mem: Add tTAW and tFAW to the SimpleDRAM model This patch adds two additional scheduling constraints to the DRAM controller model, to constrain the activation rate. The two metrics are determine the size of the activation window in terms of the number of activates and the minimum time required for that number of activates. This maps to current DDRx, LPDDRx and WIOx standards that have either tFAW (4 activate window) or tTAW (2 activate window) scheduling constraints. --- src/mem/simple_dram.hh | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'src/mem/simple_dram.hh') diff --git a/src/mem/simple_dram.hh b/src/mem/simple_dram.hh index de597d668..d8f51a745 100644 --- a/src/mem/simple_dram.hh +++ b/src/mem/simple_dram.hh @@ -46,6 +46,8 @@ #ifndef __MEM_SIMPLE_DRAM_HH__ #define __MEM_SIMPLE_DRAM_HH__ +#include + #include "base/statistics.hh" #include "enums/AddrMap.hh" #include "enums/MemSched.hh" @@ -127,6 +129,9 @@ class SimpleDRAM : public AbstractMemory */ bool stopReads; + /** List to keep track of activate ticks */ + std::deque actTicks; + /** * A basic class to track the bank state indirectly via * times "freeAt" and "tRASDoneAt" and what page is currently open @@ -323,6 +328,15 @@ class SimpleDRAM : public AbstractMemory */ Tick maxBankFreeAt() const; + + /** + * Keep track of when row activations happen, in order to enforce + * the maximum number of activations in the activation window. The + * method updates the time that the banks become available based + * on the current limits. + */ + void recordActivate(Tick act_tick); + void printParams() const; void printQs() const; @@ -381,6 +395,8 @@ class SimpleDRAM : public AbstractMemory const Tick tRP; const Tick tRFC; const Tick tREFI; + const Tick tXAW; + const uint32_t activationLimit; /** * Memory controller configuration initialized based on parameter -- cgit v1.2.3