From b47737dde7e9138a7e7511380d785f11417552d0 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Wed, 20 Jun 2007 08:14:11 -0700 Subject: Make sure all parameters have default values if they're supposed to and make sure parameters have the right type. Also make sure that any object that should be an intermediate type has the right options set. --HG-- extra : convert_revision : d56910628d9a067699827adbc0a26ab629d11e93 --- src/mem/cache/BaseCache.py | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mem') diff --git a/src/mem/cache/BaseCache.py b/src/mem/cache/BaseCache.py index 32f3f0174..55b68f81f 100644 --- a/src/mem/cache/BaseCache.py +++ b/src/mem/cache/BaseCache.py @@ -90,3 +90,4 @@ class BaseCache(MemObject): "Only prefetch on data not on instruction accesses") cpu_side = Port("Port on side closer to CPU") mem_side = Port("Port on side closer to MEM") + addr_range = VectorParam.AddrRange(AllMemory, "The address range in bytes") -- cgit v1.2.3 From d540dde5b4ed38c5aec846282082dd04fce24b78 Mon Sep 17 00:00:00 2001 From: Vincentius Robby Date: Wed, 20 Jun 2007 14:54:17 -0400 Subject: Removed "adding instead of dividing" trick. Caused slowdown in performance instead of speeding up. src/cpu/base.cc: Removed "adding instead of dividing" trick. src/mem/bus.cc: Fixed spelling in comments. Removed "adding instead of dividing" trick. --HG-- extra : convert_revision : 65a736f4f09a64e737dc7aeee53b117976330488 --- src/mem/bus.cc | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) (limited to 'src/mem') diff --git a/src/mem/bus.cc b/src/mem/bus.cc index 13e545064..806c7ed85 100644 --- a/src/mem/bus.cc +++ b/src/mem/bus.cc @@ -115,11 +115,14 @@ void Bus::occupyBus(PacketPtr pkt) //Bring tickNextIdle up to the present tick //There is some potential ambiguity where a cycle starts, which might make //a difference when devices are acting right around a cycle boundary. Using - //a < allows things which happen exactly on a cycle boundary to take up only - //the following cycle. Anthing that happens later will have to "wait" for - //the end of that cycle, and then start using the bus after that. - while (tickNextIdle < curTick) - tickNextIdle += clock; + //a < allows things which happen exactly on a cycle boundary to take up + //only the following cycle. Anything that happens later will have to "wait" + //for the end of that cycle, and then start using the bus after that. + if (tickNextIdle < curTick) { + tickNextIdle = curTick; + if (tickNextIdle % clock != 0) + tickNextIdle -= (curTick % clock) + clock; + } // The packet will be sent. Figure out how long it occupies the bus, and // how much of that time is for the first "word", aka bus width. @@ -132,10 +135,9 @@ void Bus::occupyBus(PacketPtr pkt) // We're using the "adding instead of dividing" trick again here if (pkt->hasData()) { int dataSize = pkt->getSize(); - for (int transmitted = 0; transmitted < dataSize; - transmitted += width) { + numCycles += dataSize/width; + if (dataSize % width) numCycles++; - } } else { // If the packet didn't have data, it must have been a response. // Those use the bus for one cycle to send their data. -- cgit v1.2.3 From 4a7bc06553577f25e8dc895fa20506c62455a4b6 Mon Sep 17 00:00:00 2001 From: Vincentius Robby Date: Wed, 20 Jun 2007 15:04:36 -0400 Subject: Minor error. --HG-- extra : convert_revision : 514032e21c8861f20fcbcae7204e132088cc7dbc --- src/mem/bus.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mem') diff --git a/src/mem/bus.cc b/src/mem/bus.cc index 806c7ed85..d818a25ea 100644 --- a/src/mem/bus.cc +++ b/src/mem/bus.cc @@ -121,7 +121,7 @@ void Bus::occupyBus(PacketPtr pkt) if (tickNextIdle < curTick) { tickNextIdle = curTick; if (tickNextIdle % clock != 0) - tickNextIdle -= (curTick % clock) + clock; + tickNextIdle = curTick - (curTick % clock) + clock; } // The packet will be sent. Figure out how long it occupies the bus, and -- cgit v1.2.3