From 3bc33eeaea3172fa65ec40f1e0eef9554eb51d8f Mon Sep 17 00:00:00 2001
From: Brad Beckmann <Brad.Beckmann@amd.com>
Date: Wed, 23 Feb 2011 16:41:58 -0800
Subject: ruby: cleaned up access permission enum

---
 src/mem/protocol/MESI_CMP_directory-L2cache.sm     |  2 +-
 src/mem/protocol/RubySlicc_Exports.sm              | 20 +++++++++++++-------
 src/mem/ruby/slicc_interface/AbstractCacheEntry.cc |  3 +--
 src/mem/ruby/system/PerfectCacheMemory.hh          |  2 +-
 4 files changed, 16 insertions(+), 11 deletions(-)

(limited to 'src/mem')

diff --git a/src/mem/protocol/MESI_CMP_directory-L2cache.sm b/src/mem/protocol/MESI_CMP_directory-L2cache.sm
index c037527de..aeaf3d60d 100644
--- a/src/mem/protocol/MESI_CMP_directory-L2cache.sm
+++ b/src/mem/protocol/MESI_CMP_directory-L2cache.sm
@@ -219,7 +219,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
       } else if (state == State:M) {
         cache_entry.changePermission(AccessPermission:Read_Write);
       } else if (state == State:MT) {
-        cache_entry.changePermission(AccessPermission:Stale);
+        cache_entry.changePermission(AccessPermission:Invalid);
       } else {
         cache_entry.changePermission(AccessPermission:Busy);
       }
diff --git a/src/mem/protocol/RubySlicc_Exports.sm b/src/mem/protocol/RubySlicc_Exports.sm
index 2799be55d..c02af62ef 100644
--- a/src/mem/protocol/RubySlicc_Exports.sm
+++ b/src/mem/protocol/RubySlicc_Exports.sm
@@ -47,14 +47,20 @@ external_type(DataBlock, desc="..."){
 // Declarations of external types that are common to all protocols
 
 // AccessPermission
+// The following five states define the access permission of all memory blocks.
+// These permissions have multiple uses.  They coordinate locking and 
+// synchronization primitives, as well as enable functional accesses.
+// One should not need to add any additional permission values and it is very
+// risky to do so.
 enumeration(AccessPermission, desc="...", default="AccessPermission_NotPresent") {
-  Busy,       desc="No Read or Write";
-  Read_Only,  desc="Read Only";
-  Read_Write, desc="Read/Write";
-  Invalid,    desc="Invalid";
-  NotPresent, desc="NotPresent";
-  ReadUpgradingToWrite, desc="Read only, but trying to get Read/Write";
-  Stale,      desc="local L1 has a modified copy, assume L2 copy is stale data";
+  // Valid data
+  Read_Only,  desc="block is Read Only (modulo functional writes)";
+  Read_Write, desc="block is Read/Write";
+
+  // Invalid data
+  Invalid,    desc="block is in an Invalid base state";
+  NotPresent, desc="block is NotPresent";
+  Busy,       desc="block is in a transient state, currently invalid";
 }
 
 // TesterStatus
diff --git a/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc b/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
index c0fe6ffd3..d53697c76 100644
--- a/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
+++ b/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
@@ -50,8 +50,7 @@ AbstractCacheEntry::changePermission(AccessPermission new_perm)
 {
     m_Permission = new_perm;
     if ((new_perm == AccessPermission_Invalid) ||
-        (new_perm == AccessPermission_NotPresent) ||
-        (new_perm == AccessPermission_Stale)) {
+        (new_perm == AccessPermission_NotPresent)) {
         m_locked = -1;
     }
 }
diff --git a/src/mem/ruby/system/PerfectCacheMemory.hh b/src/mem/ruby/system/PerfectCacheMemory.hh
index b04a64717..772b3d1f9 100644
--- a/src/mem/ruby/system/PerfectCacheMemory.hh
+++ b/src/mem/ruby/system/PerfectCacheMemory.hh
@@ -149,7 +149,7 @@ inline void
 PerfectCacheMemory<ENTRY>::allocate(const Address& address)
 {
     PerfectCacheLineState<ENTRY> line_state;
-    line_state.m_permission = AccessPermission_Busy;
+    line_state.m_permission = AccessPermission_Invalid;
     line_state.m_entry = ENTRY();
     m_map[line_address(address)] = line_state;
 }
-- 
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