From 271b9a5435ac26c836774b25ad1fa68e2351d25a Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Thu, 23 Nov 2006 01:42:57 -0500 Subject: first cut at a sparc tlb src/arch/sparc/SConscript: Add code to serialize/unserialze tlb entries src/arch/sparc/asi.cc: src/arch/sparc/asi.hh: update asi names for how they're listed in the supplement add asis add more asi functions src/arch/sparc/isa_traits.hh: move the interrupt stuff and some basic address space stuff into isa traits src/arch/sparc/miscregfile.cc: src/arch/sparc/miscregfile.hh: add mmu registers to tlb get rid of implicit asi stuff... the tlb will handle it src/arch/sparc/regfile.hh: make isnt/dataAsid return ints not asis src/arch/sparc/tlb.cc: src/arch/sparc/tlb.hh: first cut at sparc tlb src/arch/sparc/vtophys.hh: pagatable nedes to be included here src/mem/request.hh: add asi and if the request is a memory mapped register to the requset object src/sim/host.hh: fix incorrect definition of LL --HG-- extra : convert_revision : 6c85cd1681c62c8cd8eab04f70b1f15a034b0aa3 --- src/mem/request.hh | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'src/mem') diff --git a/src/mem/request.hh b/src/mem/request.hh index e54984fcd..5817b24e0 100644 --- a/src/mem/request.hh +++ b/src/mem/request.hh @@ -95,6 +95,11 @@ class Request /** The address space ID. */ int asid; + /** The ASI is any -- SPARC ONLY */ + int asi; + /** This request is to a memory mapped register. */ + bool mmapedReg; + /** The virtual address of the request. */ Addr vaddr; @@ -215,6 +220,16 @@ class Request /** Accessor function for asid.*/ int getAsid() { assert(validAsidVaddr); return asid; } + /** Accessor function for asi.*/ + int getAsi() { assert(validAsidVaddr); return asi; } + /** Accessor function for asi.*/ + void setAsi(int a) { assert(validAsidVaddr); asi = a; } + + /** Accessor function for asi.*/ + bool getMmapedReg() { assert(validPaddr); return mmapedReg; } + /** Accessor function for asi.*/ + void setMmapedReg(bool r) { assert(validPaddr); mmapedReg = r; } + /** Accessor function to check if sc result is valid. */ bool scResultValid() { return validScResult; } /** Accessor function for store conditional return value.*/ -- cgit v1.2.3 From b2eecd643c1706d0d070568d5370aafa3910c104 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Wed, 29 Nov 2006 17:11:10 -0500 Subject: Add support for mmapped iprs to atomic cpu src/arch/SConscript: add mmaped_ipr.hh to switch headers src/arch/sparc/asi.hh: make ASI_IMPLICT=0 so by default nothing needs to be done src/arch/sparc/miscregfile.hh: miscregfile no longer needs to include asi.hh src/arch/sparc/tlb.cc: src/arch/sparc/tlb.hh: implement panic instructions for mmaped ipr reads src/cpu/simple/atomic.cc: add check for mmaped iprs and handle them if it exists src/mem/request.hh: allocate space in the flags for mmaped iprs. Put in in the first 8 bits so that by default its fast. Move the other flags up 8 bits --HG-- extra : convert_revision : 31255b0494588c4d06a727fe35241121d741b115 --- src/mem/request.hh | 40 +++++++++++++++++++++++----------------- 1 file changed, 23 insertions(+), 17 deletions(-) (limited to 'src/mem') diff --git a/src/mem/request.hh b/src/mem/request.hh index 5817b24e0..b01c02441 100644 --- a/src/mem/request.hh +++ b/src/mem/request.hh @@ -49,26 +49,28 @@ class Request; typedef Request* RequestPtr; +/** ASI information for this request if it exsits. */ +const uint32_t ASI_BITS = 0x000FF; /** The request is a Load locked/store conditional. */ -const unsigned LOCKED = 0x001; +const uint32_t LOCKED = 0x00100; /** The virtual address is also the physical address. */ -const unsigned PHYSICAL = 0x002; +const uint32_t PHYSICAL = 0x00200; /** The request is an ALPHA VPTE pal access (hw_ld). */ -const unsigned VPTE = 0x004; +const uint32_t VPTE = 0x00400; /** Use the alternate mode bits in ALPHA. */ -const unsigned ALTMODE = 0x008; +const uint32_t ALTMODE = 0x00800; /** The request is to an uncacheable address. */ -const unsigned UNCACHEABLE = 0x010; +const uint32_t UNCACHEABLE = 0x01000; /** The request should not cause a page fault. */ -const unsigned NO_FAULT = 0x020; +const uint32_t NO_FAULT = 0x02000; /** The request should be prefetched into the exclusive state. */ -const unsigned PF_EXCLUSIVE = 0x100; +const uint32_t PF_EXCLUSIVE = 0x10000; /** The request should be marked as LRU. */ -const unsigned EVICT_NEXT = 0x200; +const uint32_t EVICT_NEXT = 0x20000; /** The request should ignore unaligned access faults */ -const unsigned NO_ALIGN_FAULT = 0x400; +const uint32_t NO_ALIGN_FAULT = 0x40000; /** The request was an instruction read. */ -const unsigned INST_READ = 0x800; +const uint32_t INST_READ = 0x80000; class Request { @@ -95,10 +97,9 @@ class Request /** The address space ID. */ int asid; - /** The ASI is any -- SPARC ONLY */ - int asi; + /** This request is to a memory mapped register. */ - bool mmapedReg; + bool mmapedIpr; /** The virtual address of the request. */ Addr vaddr; @@ -169,6 +170,7 @@ class Request validAsidVaddr = false; validPC = false; validScResult = false; + mmapedIpr = false; } /** @@ -186,6 +188,7 @@ class Request validAsidVaddr = true; validPC = true; validScResult = false; + mmapedIpr = false; } /** Set just the physical address. This should only be used to @@ -221,14 +224,17 @@ class Request int getAsid() { assert(validAsidVaddr); return asid; } /** Accessor function for asi.*/ - int getAsi() { assert(validAsidVaddr); return asi; } + uint8_t getAsi() { assert(validAsidVaddr); return flags & ASI_BITS; } + /** Accessor function for asi.*/ - void setAsi(int a) { assert(validAsidVaddr); asi = a; } + void setAsi(uint8_t a) + { assert(validAsidVaddr); flags = (flags & ~ASI_BITS) | a; } /** Accessor function for asi.*/ - bool getMmapedReg() { assert(validPaddr); return mmapedReg; } + bool isMmapedIpr() { assert(validPaddr); return mmapedIpr; } + /** Accessor function for asi.*/ - void setMmapedReg(bool r) { assert(validPaddr); mmapedReg = r; } + void setMmapedIpr(bool r) { assert(validPaddr); mmapedIpr = r; } /** Accessor function to check if sc result is valid. */ bool scResultValid() { return validScResult; } -- cgit v1.2.3