From 6f6adbf0f6a4ca96cf44a24ea575860af56eb7b2 Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Thu, 25 Oct 2012 13:14:44 -0400 Subject: dev: Make default clock more reasonable for system and devices This patch changes the default system clock from 1THz to 1GHz. This clock is used by all modules that do not override the default (parent clock), and primarily affects the IO subsystem. Every DMA device uses its clock to schedule the next transfer, and the change will thus cause this inter-transfer delay to be longer. The default clock of the bus is removed, as the clock inherited from the system provides exactly the same value. A follow-on patch will bump the stats. --- src/mem/Bus.py | 2 -- 1 file changed, 2 deletions(-) (limited to 'src/mem') diff --git a/src/mem/Bus.py b/src/mem/Bus.py index 447fc723e..45b1f1b0a 100644 --- a/src/mem/Bus.py +++ b/src/mem/Bus.py @@ -47,8 +47,6 @@ class BaseBus(MemObject): abstract = True slave = VectorSlavePort("vector port for connecting masters") master = VectorMasterPort("vector port for connecting slaves") - # Override the default clock - clock = '1GHz' header_cycles = Param.Cycles(1, "cycles of overhead per transaction") width = Param.Unsigned(8, "bus width (bytes)") block_size = Param.Unsigned(64, "The default block size if not set by " \ -- cgit v1.2.3