From 780aa0a0ebb765781a31d0fb58257b1efb1f324a Mon Sep 17 00:00:00 2001
From: Ron Dreslinski <rdreslin@umich.edu>
Date: Thu, 19 Oct 2006 21:26:46 -0400
Subject: Fix corner case on assertion. I need to move over to using the
 fixPacket function so I don't have to make the same changes everywhere. Still
 a functional access bug someplace I need to track down in timing mode.

src/mem/cache/base_cache.cc:
src/mem/cache/cache_impl.hh:
    Fix corner case on assertion
tests/configs/memtest.py:
    Updated memtester with uncacheable addresses and functional accesses

--HG--
extra : convert_revision : e6fa851621700ff9227b83cc5cac20af4fc8444f
---
 src/mem/cache/base_cache.cc | 2 +-
 src/mem/cache/cache_impl.hh | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

(limited to 'src/mem')

diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc
index 936a9c1fa..e0301a757 100644
--- a/src/mem/cache/base_cache.cc
+++ b/src/mem/cache/base_cache.cc
@@ -132,7 +132,7 @@ BaseCache::CachePort::recvFunctional(Packet *pkt)
                 pkt_data = pkt->getPtr<uint8_t>() + offset;
                 write_data = target->getPtr<uint8_t>();
                 data_size = pkt->getSize() - offset;
-                assert(data_size > pkt->getSize());
+                assert(data_size >= pkt->getSize());
                 if (data_size > target->getSize())
                     data_size = target->getSize();
             }
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index d8afcb009..ea30dbba6 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -585,7 +585,7 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update,
                         pkt_data = pkt->getPtr<uint8_t>() + offset;
                         write_data = target->getPtr<uint8_t>();
                         data_size = pkt->getSize() - offset;
-                        assert(data_size > pkt->getSize());
+                        assert(data_size >= pkt->getSize());
                         if (data_size > target->getSize())
                             data_size = target->getSize();
                     }
@@ -620,7 +620,7 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update,
                     pkt_data = pkt->getPtr<uint8_t>() + offset;
                     write_data = write->getPtr<uint8_t>();
                     data_size = pkt->getSize() - offset;
-                    assert(data_size > pkt->getSize());
+                    assert(data_size >= pkt->getSize());
                     if (data_size > write->getSize())
                         data_size = write->getSize();
                 }
-- 
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