From 7e00772bda1a1c74fe659c56fea803642302c1da Mon Sep 17 00:00:00 2001 From: David Hashe Date: Mon, 20 Jul 2015 09:15:18 -0500 Subject: ruby: speed up function used for cache walks This patch adds a few helpful functions that allow .sm files to directly invalidate all cache blocks using a trigger queue rather than rely on each individual cache block to be invalidated via requests from the mandatory queue. --- src/mem/protocol/RubySlicc_Types.sm | 5 +++++ src/mem/ruby/structures/CacheMemory.cc | 24 ++++++++++++++++++++++++ src/mem/ruby/structures/CacheMemory.hh | 5 +++++ 3 files changed, 34 insertions(+) (limited to 'src/mem') diff --git a/src/mem/protocol/RubySlicc_Types.sm b/src/mem/protocol/RubySlicc_Types.sm index 88b9839bb..51f99b603 100644 --- a/src/mem/protocol/RubySlicc_Types.sm +++ b/src/mem/protocol/RubySlicc_Types.sm @@ -1,5 +1,6 @@ /* * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood + * Copyright (c) 2013 Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -155,6 +156,10 @@ structure (CacheMemory, external = "yes") { void recordRequestType(CacheRequestType); bool checkResourceAvailable(CacheResourceType, Address); + int getCacheSize(); + int getNumBlocks(); + Address getAddressAtIdx(int); + Scalar demand_misses; Scalar demand_hits; } diff --git a/src/mem/ruby/structures/CacheMemory.cc b/src/mem/ruby/structures/CacheMemory.cc index 047c024c9..486b5ae97 100644 --- a/src/mem/ruby/structures/CacheMemory.cc +++ b/src/mem/ruby/structures/CacheMemory.cc @@ -1,5 +1,6 @@ /* * Copyright (c) 1999-2012 Mark D. Hill and David A. Wood + * Copyright (c) 2013 Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -134,6 +135,29 @@ CacheMemory::findTagInSetIgnorePermissions(int64 cacheSet, return -1; // Not found } +// Given an unique cache block identifier (idx): return the valid address +// stored by the cache block. If the block is invalid/notpresent, the +// function returns the 0 address +Address +CacheMemory::getAddressAtIdx(int idx) const +{ + Address tmp(0); + + int set = idx / m_cache_assoc; + assert(set < m_cache_num_sets); + + int way = idx - set * m_cache_assoc; + assert (way < m_cache_assoc); + + AbstractCacheEntry* entry = m_cache[set][way]; + if (entry == NULL || + entry->m_Permission == AccessPermission_Invalid || + entry->m_Permission == AccessPermission_NotPresent) { + return tmp; + } + return entry->m_Address; +} + bool CacheMemory::tryCacheAccess(const Address& address, RubyRequestType type, DataBlock*& data_ptr) diff --git a/src/mem/ruby/structures/CacheMemory.hh b/src/mem/ruby/structures/CacheMemory.hh index a777538b2..82bb65776 100644 --- a/src/mem/ruby/structures/CacheMemory.hh +++ b/src/mem/ruby/structures/CacheMemory.hh @@ -1,5 +1,6 @@ /* * Copyright (c) 1999-2012 Mark D. Hill and David A. Wood + * Copyright (c) 2013 Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -131,6 +132,10 @@ class CacheMemory : public SimObject Stats::Scalar numTagArrayStalls; Stats::Scalar numDataArrayStalls; + int getCacheSize() const { return m_cache_size; } + int getNumBlocks() const { return m_cache_num_sets * m_cache_assoc; } + Address getAddressAtIdx(int idx) const; + private: // convert a Address to its location in the cache int64 addressToCacheSet(const Address& address) const; -- cgit v1.2.3