From de2321de81506a81f64641babe0bce17ab946b9c Mon Sep 17 00:00:00 2001
From: Steve Reinhardt <steve.reinhardt@amd.com>
Date: Tue, 22 Jun 2010 21:29:43 -0700
Subject: cache: fix longstanding prefetcher bug Thanks to Joe Gross for
 pointing this out (again?). Apologies to anyone who pointed it out earlier
 and we didn't listen.

---
 src/mem/cache/cache_impl.hh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/mem')

diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index d5eb38e48..8ff11b26f 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -1308,7 +1308,7 @@ Cache<TagStore>::getNextMSHR()
 
     // fall through... no pending requests.  Try a prefetch.
     assert(!miss_mshr && !write_mshr);
-    if (!mshrQueue.isFull()) {
+    if (prefetcher && !mshrQueue.isFull()) {
         // If we have a miss queue slot, we can try a prefetch
         PacketPtr pkt = prefetcher->getPacket();
         if (pkt) {
-- 
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