From 344f72dd62f6cc9ab8c7ab5454a320b2e5674a37 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Wed, 8 Nov 2006 13:04:36 -0500 Subject: Remove mem parameter. Should have been removed earlier. src/python/m5/objects/BaseCPU.py: These parameters should have been removed in an earlier push. --HG-- extra : convert_revision : 781b39ca370361e9568b1af0be96ff5848b1f3f4 --- src/python/m5/objects/BaseCPU.py | 2 -- 1 file changed, 2 deletions(-) (limited to 'src/python/m5/objects/BaseCPU.py') diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py index b6dc08e46..4e34e8a4e 100644 --- a/src/python/m5/objects/BaseCPU.py +++ b/src/python/m5/objects/BaseCPU.py @@ -8,7 +8,6 @@ from Bus import Bus class BaseCPU(SimObject): type = 'BaseCPU' abstract = True - mem = Param.MemObject("memory") system = Param.System(Parent.any, "system object") cpu_id = Param.Int("CPU identifier") @@ -47,7 +46,6 @@ class BaseCPU(SimObject): self.icache_port = ic.cpu_side self.dcache_port = dc.cpu_side self._mem_ports = ['icache.mem_side', 'dcache.mem_side'] -# self.mem = dc def addTwoLevelCacheHierarchy(self, ic, dc, l2c): self.addPrivateSplitL1Caches(ic, dc) -- cgit v1.2.3